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Study of Accelerated Soft Error Rate for Cell Characteristics on Static RAM  

Gong, Myeong-Kook ((주)옵토웨이)
Wang, Jin-Suk (충남대학교)
Kim, Do-Woo (안성여자기능대학)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers C / v.55, no.3, 2006 , pp. 111-115 More about this Journal
Abstract
We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.
Keywords
Accelerated Soft Error Rate; Buried Well; Cell Transistor; Static RAM;
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Times Cited By KSCI : 1  (Citation Analysis)
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