• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.175-177
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• 2011

오늘날 반도체 소자의 성능을 좌우하는 배선폭은 수십 나노미터급으로 배선폭 감소에 의한 소자의 집적은 한계에 다다르고 있다. 또한 2차원 회로 소자의 문제점으로 지적되는 과도한 전력소모, RC Delay, 열 발생 문제등도 쟁점사항이 되고 있다. 이런 2차원 회로를 3차원으로 쌓아올린다면 보다 효율적인 회로구성이 가능할 것이고 이에 따른 성능향상이 클 것이다. 3차원 회로 구성의 핵심기술은 기판을 관통하여 다른 층의 회로를 연결하는 실리콘 관통 전극을 형성하는 것이다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.137-137
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• 2010

Copper electroplating is a very popular and important technology for depositing high-quality conductor interconnections, especially in through silicon via (TSV). As this advanced packaging technique developing, a mass of copper and chemical solution are used, so attention to these chemical materials into the utilization and costs can not be ignored. An economical and practical real-time chemical solution monitoring has not been achieved yet. Either Red-green-blue (RGB) or optical emission spectroscopy (OES) color sensor can successfully monitor the color condition of solution during the process. The reaction rate, uniformity and quality can map onto the color changing. Hidden Semi Markov model (HSMM) can establish mapping from the color change to upper indicators, and artificial neural network (ANN) can be integrated to comprehensively determine its targets, whether the solution inside the container can continue to use.

• Journal of the Korea Organic Resources Recycling Association
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• v.31 no.3
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• pp.35-41
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• 2023

In this study, silicon sludge generated in semiconductor manufacturing process is recycled and applied as materials for pigments and paints. In detail, metallic impurities are removed from silicon sludge to obtain plate-like silicon sludge powder (SW-sludge), which is then coated with titanium dioxide via sol-gel method (TCS-sludge). SW-sludge and TCS-sludge are dispersed in hydrophilic transparent varnish and sprayed onto glass substrates to observe the possibility for the application as materials for pigments and paints. Notably, the applicability of TCS-sludge-based paint is improved compared to SW-sludge-based paint after the titanium dioxide coating. Moreover, the color of TCS-sludge-based paint turns into white. Accordingly, it is confirmed that the applicability and hydrophilicity are improved by the presence of outer titanium dioxide layer. In this regard, it is expected that the recycled TCS-sludge may be a future material for the application as pigments and paints.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1449-1450
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• 2011

The SiC-$ZrB_2$ composites were produced by subjecting a 40:60 (vol.%) mixture of zirconium diboride($ZrB_2$) powder and ${\beta}$-silicon carbide (SiC) matrix to spark plasma sintering(SPS) under argon atmosphere at 50MPa(P50) and 60MPa(P60) pressure. The relative density, 94.13% of P60 sample was lower than that, 94.75% of P50 sample. Reactions between ${\beta}$-SiC and $ZrB_2$ were not observed via x-ray diffraction (hereafter, XRD) analysis. The trend of flexural strength of SiC-$ZrB_2$ composites were in accordance with the relative density. The properties of a SiC-$ZrB_2$ composites through SPS under argon atmosphere were positive temperature coefficient resistance in the temperature range from $25^{\circ}C$ to $500^{\circ}C$, and electrical resistivity of P50 and P60 sample were $6.75{\times}10^{-4}$ and $7.22{\times}10^{-4}{\Omega}{\cdot}cm$ at room temperature, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.131-136
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• 2013

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

• ETRI Journal
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• v.41 no.3
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• pp.396-407
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• 2019

Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

• Journal of Microbiology and Biotechnology
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• v.16 no.12
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• pp.1968-1976
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• 2006

Recombinant E. coli ACV 1003 (recA:: lacZ) was used to measure low concentrations of DNA-damaging chemicals, which produce $\beta$-galactosidase via an SOS regulon system. Very low $\beta$-galactosidase activities of less than 0.01 unit/ml, $\beta$-galactosidase produced through an SOS response corresponding to the 10 ng/ml (ppb) of DNA damaging chemicals in the environment, can be rapidly determined by using an alternative interferometric biosensor with optically flat thin films of porous silicon rather than by the conventional time-consuming Miller's enzyme assay as well as the ELISA method. fu order to enhance the sensitivity in the interferometry, it needs to obtain more uniform distribution and higher biolinking efficiency, whereas interferometric sensing is rapid, cheap, and advantageous in high throughput by using a multiple-well-type chip. In this study, pore size adjusted to 60 nm for the target enzyme $\beta$-galactosidase to be bound on both walls of a Si pore and a calyx crown derivative was apllied as a more efficient biolinker. Furthermore, anti-$\beta$-galactosidase was previously functionalized with the biolinker for the target $\beta$-galactosidase to be specifically bound. When anti-$\beta$-galactosidase was bound to the calyx-crown derivative-linked surface, the effective optical thickness was found to be three times as high as that obtained without using anti-$\beta$-galactosidase. The resolution obtained was very similar to that afforded by the time-consuming ELISA method; however, the reproducibility was still unsatisfactory, below 1 unit $\beta$-galactosidase/ml, owing to the microscopic non-uniform distribution of the pores in the etched silicon surface.