• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.39-43
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• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.15-16
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• 2008

In case manufacturing COF, through hole should be made to be used for a pathway connecting the conductive layers of its both faces. In case Cu-plating inside of through hole with electroless plating way, contact between Cu and PI film gets bad to be fell apart from PI by the impact of applying to the electric devices. Therefore, after sputtering is applying on inner through hole, then a method to perform electroplating process. In this study, after changing sputtering condition to manufacture FCCL, we looked the changeability of the upper PI and inner hole Cu layers. Making use of RF Magnetron sputtering equipment, we coated Cu thin film and Cu-plated on it through electroplating. After cold-mounting the completed FCCL, we examined hole section through an optical microscope. From the result of test, with parameters deposition pressure and deposition time, both the thickness of the hole plated layer and PI plated upper layer increased at regular rate, increasing the thickness of Cu sputter layer. However, from the result of test in increasing RF-power, we could know the increment rate of hole plated layer is considerably greater than that of PI plated upper layer. Therefore, we finally acquired good result; if you want only to increase the plated layer of inner hole, it's much better to increase RF-power.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.78-81
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• 2008

A hollow cathode which has extremely stable discharge characteristic has been developed. This is composed of the two separated lanthanum hexaboride(LaB6) of a disk type in the tube as the electron emitters. The way of design is of great advantage to extend the surface discharge area of the LaB6, which is also useful for optimal fixing of the LaB6. The hollow cathode is capable of producing 30 kW(100 V, 300 A) of power continuously. Because the generated plasma beam with the high temperature(above $3000^{\circ}C$) from the hollow cathode passes through the center hole of the two intermediate electrodes, it is designed with the high temperature material of the tungsten and the suitable structure of the water cooling. The combinations of the hollow cathode and the two intermediate electrodes are practically useful for the ion plating plasma beam source.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.45-51
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• 2021

The purpose of this study is to suggest the optimal shape for a local air ventilation system for fume removal, which is operated in a zinc galvanizing factory, and to propose the improvement plan for a ventilation system used in a zinc galvanizing factory through flow analysis. A part of the air sprayed by an air curtain goes out. It will be necessary to research the position of an air curtain, its spray angles, and its nozzle shape. In addition, additional research needs to be conducted on the shape of the fan installed before a hood in order to make it easy to induce fume. In a local air ventilation system, air is inhaled from the outside. The higher an inlet negative pressure is, the easier fume is removed. It was found that it was necessary to install an appropriate hole in the wall on the back of a push nozzle in order to reduce an inlet negative pressure.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Corrosion Science and Technology
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• v.10 no.4
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• pp.143-150
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• 2011

Copper electroplating has been applied to various fields such as decorative plating and through-hole plating. Technical realization of high strength copper preplating for wear-resistant tools and molds in addition to these applications is the aim of this work. Brighters and levelers, such as MPSA, Gelatin, Thiourea, PEG and JGB, were added in copper sulfate electrolyte, and the effects of these organic additives on the hardness were evaluated. All additives in this work were effective in increasing the hardness of copper electrodeposits. Thiourea increased the hardness up to 350 VHN, and was the most effective accelarator in sulfate electrolyte. It was shown from the X-ray diffraction analysis that preferred orientation changed from (200) to (111) with increasing concentration of organic additives. Crystallite size decreased with increasing concentration of additive. Hardness was increased with decreasing crystallite size, and this result is consistent with Hall-Petch relationship, and it was apparent that the hardening of copper electrodeposits results from the grain refining effect.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.903-906
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• 2011

The electroplating and electro-less plating methods have been applied for the high density chip interconnect of the Copper Pillar Tin Bump (CPTB) preparation. The CPTB was prepared, which had been electroplated about $100{\mu}m$ pitch of copper layer firstly, and then the Tin layer was deposited on the copper pillar surface to protect the oxidation of it. It was also very important to get uniform thickness of electroplated copper layer, though it was difficult and sensitive. In order to control the thickness distribution, it was examined that the current separating disk of Insulating Gate with a hole in the center was installed between electrodes. The current flows through the center hole of the Insulating Gate in the cylindrical electroplating bath and the other parts were blocked to protect current flowing. The main current flowed through the center hole of the Insulating Gate directly to the opposite electrode of wafer disk. As the results, it was verified that the copper layer was thick in the center part of wafer disk with distribution of thinner to the outer part toward edge.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.