• 마이크로전자및패키징학회지
• /
• 제19권4호
• /
• pp.39-43
• /
• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2008년도 추계학술대회 초록집
• /
• pp.15-16
• /
• 2008

In case manufacturing COF, through hole should be made to be used for a pathway connecting the conductive layers of its both faces. In case Cu-plating inside of through hole with electroless plating way, contact between Cu and PI film gets bad to be fell apart from PI by the impact of applying to the electric devices. Therefore, after sputtering is applying on inner through hole, then a method to perform electroplating process. In this study, after changing sputtering condition to manufacture FCCL, we looked the changeability of the upper PI and inner hole Cu layers. Making use of RF Magnetron sputtering equipment, we coated Cu thin film and Cu-plated on it through electroplating. After cold-mounting the completed FCCL, we examined hole section through an optical microscope. From the result of test, with parameters deposition pressure and deposition time, both the thickness of the hole plated layer and PI plated upper layer increased at regular rate, increasing the thickness of Cu sputter layer. However, from the result of test in increasing RF-power, we could know the increment rate of hole plated layer is considerably greater than that of PI plated upper layer. Therefore, we finally acquired good result; if you want only to increase the plated layer of inner hole, it's much better to increase RF-power.

• 전기학회논문지
• /
• 제57권1호
• /
• pp.78-81
• /
• 2008

A hollow cathode which has extremely stable discharge characteristic has been developed. This is composed of the two separated lanthanum hexaboride(LaB6) of a disk type in the tube as the electron emitters. The way of design is of great advantage to extend the surface discharge area of the LaB6, which is also useful for optimal fixing of the LaB6. The hollow cathode is capable of producing 30 kW(100 V, 300 A) of power continuously. Because the generated plasma beam with the high temperature(above $3000^{\circ}C$) from the hollow cathode passes through the center hole of the two intermediate electrodes, it is designed with the high temperature material of the tungsten and the suitable structure of the water cooling. The combinations of the hollow cathode and the two intermediate electrodes are practically useful for the ion plating plasma beam source.

• 한국산업융합학회 논문집
• /
• 제24권1호
• /
• pp.45-51
• /
• 2021

The purpose of this study is to suggest the optimal shape for a local air ventilation system for fume removal, which is operated in a zinc galvanizing factory, and to propose the improvement plan for a ventilation system used in a zinc galvanizing factory through flow analysis. A part of the air sprayed by an air curtain goes out. It will be necessary to research the position of an air curtain, its spray angles, and its nozzle shape. In addition, additional research needs to be conducted on the shape of the fan installed before a hood in order to make it easy to induce fume. In a local air ventilation system, air is inhaled from the outside. The higher an inlet negative pressure is, the easier fume is removed. It was found that it was necessary to install an appropriate hole in the wall on the back of a push nozzle in order to reduce an inlet negative pressure.

• Journal of Welding and Joining
• /
• 제32권3호
• /
• pp.11-18
• /
• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• 센서학회지
• /
• 제22권2호
• /
• pp.130-135
• /
• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Corrosion Science and Technology
• /
• 제10권4호
• /
• pp.143-150
• /
• 2011

Copper electroplating has been applied to various fields such as decorative plating and through-hole plating. Technical realization of high strength copper preplating for wear-resistant tools and molds in addition to these applications is the aim of this work. Brighters and levelers, such as MPSA, Gelatin, Thiourea, PEG and JGB, were added in copper sulfate electrolyte, and the effects of these organic additives on the hardness were evaluated. All additives in this work were effective in increasing the hardness of copper electrodeposits. Thiourea increased the hardness up to 350 VHN, and was the most effective accelarator in sulfate electrolyte. It was shown from the X-ray diffraction analysis that preferred orientation changed from (200) to (111) with increasing concentration of organic additives. Crystallite size decreased with increasing concentration of additive. Hardness was increased with decreasing crystallite size, and this result is consistent with Hall-Petch relationship, and it was apparent that the hardening of copper electrodeposits results from the grain refining effect.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2011년도 추계학술대회
• /
• pp.903-906
• /
• 2011

고밀도집적을 위한 구리기둥주석범프(CPTB)의 제작공정에 흔히 전기도금과 무전해도금이 적용된다. CPTB는 약 $100{\mu}m$ 정도의 피치를 갖도록 먼저 구리도금 층을 전착시킨 다음, 구리의 산화 억제를 위하여 구리기둥 주위에 주석을 입혀 제작한다. 이 과정에서 구리도금 층 두께를 균일하게 형성하는 일은 매우 민감하고 어렵지만 중요한 일이다. 이를 위하여 구리도금 전극 사이에 전류분포 제어를 위한 절연 막(절연게이트)을 형성하여 도금 층의 두께분포를 조절하는 실험을 하였다. 원통형 도금 조에서 중심부를 열어 전류를 흘려주고, 그 외 부분은 가장자리 끝까지 막고 전류를 차단하여 두께분포 변화를 확인하였다.

• 한국전기전자재료학회논문지
• /
• 제15권10호
• /
• pp.889-895
• /
• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• 마이크로전자및패키징학회지
• /
• 제21권4호
• /
• pp.91-96
• /
• 2014

TSV기술은 실리콘 칩에 관통 홀(through silicon via)을 형성하고, 비아 내부에 전도성 금속으로 채워 수직으로 쌓아 올려 칩의 집적도를 향상시키는 3차원 패키징 기술로서, 와이어 본딩(wire bonding)방식으로 접속하는 기존의 방식에 비해 배선의 거리를 크게 단축시킬 수 있다. 이를 통해 빠른 처리 속도, 낮은 소비전력, 높은 소자밀도를 얻을 수 있다. 본 연구에서는 웨이퍼 레벨에서의 TSV 충전 경향을 조사하기 위하여, 실리콘의 칩 레벨에서부터 4" 웨이퍼까지 전해 도금법을 이용하여 Cu를 충전하였다. Cu 충전을 위한 도금액은 CuSO4 5H2O, H2SO4 와 소량의 첨가제로 구성하였다. 양극은 Pt를 사용하였으며, 음극은 $0.5{\times}0.5 cm^2{\sim}5{\times}5cm^2$ 실리콘 칩과 4" 실리콘 wafer를 사용하였다. 실험 결과, $0.5{\times}0.5cm^2$ 실리콘 칩을 이용하여 양극과 음극과의 거리에 따라 충전률을 비교하여 전극간 거리가 4 cm일 때 충전률이 가장 양호하였다. $5{\times}5cm^2$ 실리콘 칩의 경우, 전류 공급위치로부터 0~0.5 cm 거리에 위치한 TSV의 경우 100%의 Cu충전률을 보였고, 4.5~5 cm 거리에 위치한 TSV의 경우 충전률이 약 95%로 비아의 입구 부분이 완전히 충전되지 않는 경향을 보였다. 전극에서 멀리 떨어져있는 TSV에서 Cu 충전률이 감소하였으며, 안정된 충전을 위하여 전류를 인가하는 시간을 2 hrs에서 2.5 hrs로 증가시켜 4" 웨이퍼에서 양호한 TSV 충전을 할 수 있었다.