Thickness Control of Electroplating Layer for Copper Pillar Tin Bump

구리기둥범프 용 전해도금 층 제어

The electroplating and electro-less plating methods have been applied for the high density chip interconnect of the Copper Pillar Tin Bump (CPTB) preparation. The CPTB was prepared, which had been electroplated about $100{\mu}m$ pitch of copper layer firstly, and then the Tin layer was deposited on the copper pillar surface to protect the oxidation of it. It was also very important to get uniform thickness of electroplated copper layer, though it was difficult and sensitive. In order to control the thickness distribution, it was examined that the current separating disk of Insulating Gate with a hole in the center was installed between electrodes. The current flows through the center hole of the Insulating Gate in the cylindrical electroplating bath and the other parts were blocked to protect current flowing. The main current flowed through the center hole of the Insulating Gate directly to the opposite electrode of wafer disk. As the results, it was verified that the copper layer was thick in the center part of wafer disk with distribution of thinner to the outer part toward edge.

고밀도집적을 위한 구리기둥주석범프(CPTB)의 제작공정에 흔히 전기도금과 무전해도금이 적용된다. CPTB는 약 $100{\mu}m$ 정도의 피치를 갖도록 먼저 구리도금 층을 전착시킨 다음, 구리의 산화 억제를 위하여 구리기둥 주위에 주석을 입혀 제작한다. 이 과정에서 구리도금 층 두께를 균일하게 형성하는 일은 매우 민감하고 어렵지만 중요한 일이다. 이를 위하여 구리도금 전극 사이에 전류분포 제어를 위한 절연 막(절연게이트)을 형성하여 도금 층의 두께분포를 조절하는 실험을 하였다. 원통형 도금 조에서 중심부를 열어 전류를 흘려주고, 그 외 부분은 가장자리 끝까지 막고 전류를 차단하여 두께분포 변화를 확인하였다.