• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.291.2-291.2
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• 2016

3D semiconductor material of silicon that is used throughout the semiconductor industry currently faces a physical limitation of the development of semiconductor process technology. The research into the next generation of nano-semiconductor materials such as semiconductor properties superior to replace silicon in order to overcome the physical limitations, such as the 2-dimensional graphene material in 2D transition-metal dichalcogenide (TMD) has been researched. In particular, 2D TMD doping without severely damage of crystal structure is required different conventional methods such as ion implantation in 3D semiconductor device. Here, we study a p-type doping technique on tungsten diselenide (WSe2) for p-channel 2D transistors by adjusting the concentration of hydrochloric acid through Raman spectroscopy and electrical/optical measurements. Where the performance parameters of WSe2 - based electronic device can be properly designed or optimized. (on currents increasing and threshold voltage positive shift.) We expect that our p-doping method will make it possible to successfully integrate future layered semiconductor devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.120.1-120.1
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• 2015

We investigate the degradation pattern of Black phosphorus (BP) field effect transistor (FETs) investigated by using an mechanically exfoliated BP that react O2 and water vapor in ambient condition, degradation. The BP FETs was electrically measured every 20 minutes (1cycle) in the air, the total cycle is 100. We show electrical changes with Mobility, On/off ratio, Current and a significant positive shift in the threshold voltage. We extracted the current level at Vgs-Vth = 0, -10, -20 and fitting with Swiss-cheese model. This model suggested that Swiss-cheese model is well fitted with degradation pattern of BP FETs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.167.1-167.1
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• 2015

We investigate the degradation pattern of Black phosphorus (BP) field effect transistor (FETs) was investigated by using an mechanically exfoliated BP that react O2 and water vapor in ambient condition, degradation. The BP FETs was electrically measured every 20 minutes (1cycle) in the air, the total cycle is 100. We show electrical changes with Mobility, On/off ratio, Current and a significant positive shift in the threshold voltage. We extracted the current level at Vgs-Vth = 0, -10, -20 and fitting with Swiss-cheese model. This model suggested that Swiss-cheese model is well fitted with degradation pattern of BP FETs.

• 전기학회논문지
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• 제66권9호
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• pp.1351-1358
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• 2017

In this work, we investigated radiation hardness of GaN-based transistors which are strong candidates for next-generation power electronics. Field effect transistors with three types of gate structures including metal Schottky gate, recessed gate, and p-AlGaN layer gate were fabricated on AlGaN/GaN heterostructure on Si substrate. The devices were irradiated with energetic protons and alpha-particles. The irradiated transistors exhibited the reduction of on-current and the shift of threshold voltage which were attributed to displacement damage by incident energetic particles at high fluence. However, FET operation was still maintained and leakage characteristics were not degraded, suggesting that GaN-based FETs possess high potential for radiation-hardened electronics.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1348-1351
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• 2007

We demonstrated that the threshold voltage shift owing to a gate-bias stress is originated from the trapped charges at the interface between semiconductor layer and dielectric layer, and such drawback can be settled by applying long-term delay time to the gate electrode.

• 전자공학회논문지A
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• 제31A권1호
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• pp.39-47
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• 1994

The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.197-200
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• 2008

We propose a novel n-type a-Si:H TFT pixel circuit which is proper to AMOLED display for the large size and high resolution. Proposed pixel circuit will be suit to panel for the high resolution because of different threshold sampling method. Driving method of proposed pixel circuit is very simple like an AMLCD. Our simulation indicates that the proposed pixel circuit can compensate the Vth shift and IR rising of power line so that provide better quality image.

• Journal of Information Display
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• 제9권2호
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• pp.5-8
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• 2008

Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.52-55
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• 2006

The driving-current degradation of a-Si:H thin-film transistor(TFT) device has been analyzed for the first time. A method to analyze the performance of TFT circuits is presented, which is different from the conventional one by threshold voltage shift method. It can be also used to evaluate the performance of gate driver on array (GOA) circuit, which is integrated in a 12.1" WXGA ($1280{\ast}3{\ast}800$) TFT-LCD panel.