Journal of Information Display

The Korean Infomation Display Society (한국정보디스플레이학회)
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Electrical Analysis of Bottom Gate TFT with Novel Process Architecture

  • Pak, Sang-Hoon (School of Electrical and Electronic Engineering Yonsei University) ;
  • Jeong, Tae-Hoon (School of Electrical and Electronic Engineering Yonsei University) ;
  • Kim, Si-Joon (School of Electrical and Electronic Engineering Yonsei University) ;
  • Kim, Kyung-Ho (School of Electrical and Electronic Engineering Yonsei University) ;
  • Kim, Hyun-Jae (School of Electrical and Electronic Engineering Yonsei University)
  • Published : 2008.06.30
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Abstract

Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.

Keywords

References

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