• 센서학회지
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• 제29권4호
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• 접착 및 계면
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• 제20권4호
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• pp.155-161
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• 2019

공액분자 나노구조체 계면에서의 전하이동 이방성을 이해하는 것은 유기전계효과트랜지스터(OFET)에서 구조-물성 상관관계를 규명하는데 중요하다. 본 연구에서는 대표적인 코페이셜 적층구조를 가진 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) 유기반도체 단결정과 산화물 계면에서 전하이동도 이방성을 연구하였다. 용매치환공정을 이용해 유기단결정을 산화실리콘 절연체 표면에 성장시키고 유기단결정/산화물 계면에서 전하이동을 유도할 수 있도록 OFET 소자를 완성하였다. TIPS-pentacene OFET에서 최고/최저 전하이동도 이방성은 5.2로 관찰되었다. TIPS-pentacene의 전하이동을 담당하는 공액부의 최인접부와의 상호작용을 분석한 결과, HOMO 준위 커플링과 전하의 호핑 궤도가 전하이동도 이방성에 기여하는 것으로 밝혀졌다. HOMO 준위 커플링에 기반한 전하이동도 이방성의 정량적 예측은 실험결과와 유사하게 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Transactions on Electrical and Electronic Materials
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• 제18권3호
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• pp.155-158
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• 2017

In this paper, ZnO Thin Film Transistors (TFTs) were fabricated by a sol-gel method using a low-temperature process, and their physical and electrical characteristics were analyzed. To lower the process temperature to $200^{\circ}C$, we used a zinc nitrate hydrate ($Zn(NO_3)_2{\cdot}xH_2O$) precursor. Thermo Gravimetric Analyzer (TGA) analysis showed that the zinc nitrate hydrate precursor solution had 1.5% residual organics, much less than the 6.5% of zinc acetate dihydrate at $200^{\circ}C$. In the sol-gel method, organic materials in the precursor disrupt formation of a high-quality film, and high-temperature annealing is needed to remove the organic residuals, which implies that, by using zinc nitrate hydrate, ZnO devices can be fabricated at a much lower temperature. Using an X-Ray Diffractometer (XRD) and an X-ray Photoelectron Spectrometer (XPS), $200^{\circ}C$ annealed ZnO film with zinc nitrate hydrate (ZnO (N)) was found to have an amorphous phase and much more oxygen vacancy ($V_o$) than Zn-O bonds. Despite no crystallinity, the ZnO (N) had conductance comparable to that of ZnO with zinc acetate dihydrate (ZnO (A)) annealed at $500^{\circ}C$ as in TFTs. These results show that sol-gel could be made a potent process for low-cost and flexible device applications by optimizing the precursors.

• 대한금속재료학회지
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• 제50권4호
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• pp.331-337
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• 2012

Electrical properties as a function of composition in silicon nitride ($SiN_x$) films grown at low temperatures ($<200^{\circ}C$) were studied for applications to photonic devices and thin film transistors. Both silicon-rich and nitrogen-rich compositions were successfully produced in final films by controlling the source gas mixing ratio, $R=[(N_2\;or\;NH_3)/SiH_4]$, and the RF plasma power. Depending on the film composition, the dielectric and optical properties of $SiN_x$ films varied substantially. Both the resistivity and breakdown field strength showed the maximum value at the stoichiometric composition (N/Si = 1.33), and degraded as the composition deviated to either side. The electrical properties degraded more rapidly when the composition shifted toward the silicon-rich side than toward the nitrogen-rich side. The composition shift from the silicon-rich side to the nitrogen-rich side accompanied the shift in the photoluminescence characteristic peak to a shorter wavelength, indicating an increase in the band gap. As long as the film composition is close to the stoichiometry, the breakdown field strength and the bulk resistivity showed adequate values for use as a gate dielectric layer down to $150^{\circ}C$ of the process temperature.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1750-1752
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• 1999

An active-matrix liquid crystal display (LCD) using thin film transistors (TFTs) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the sate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed. The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.41-41
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• 2009

We utilized atomic layer deposition (ALD) for the growth of the ZnO channel layers in the oxide thin-film-transistors (TFTs) with a bottom-gate structure using a $SiO_2/p-Si$ substrate. For fundamental study, the effect of the channel thickness and thermal treatment on the TFT performance was investigated. The growth modes for the ALD grown ZnO layer changed from island growth to layer-by-layer growth at thicknesses of > 7.5 nm with highly resistive properties. A channel thickness of 17 nm resulted in the good TFT behavior with an onloff current ratio of > $10^6$ and a field effect mobility of 2.9 without the need for thermal annealing. However, further increases in the channel thickness resulted in a deterioration of the TFT performance or no saturation. The ALD grown ZnO layers showed reduced electrical resistivity and carrier density after thermal treatment in oxygen.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.881-884
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• 2004

The robust and large-area applicable metal shadow masks with a high aspect ratio more than 20 are fabricated by a combination of micro-electro-discharge machining (${\mu}$-EDM) and electro chemical etching (ECE). After defining S/D contacts using a 100 ${\mu}m$ thick stainless steel shadow mask, the top-contact pentacene TFTs with channel length of 5 ${\mu}m$ showed routinely the results of mobility of 0.498 ${\pm}$ 0.05 $cm^2$/Vsec, current on/off ratio of 1.6 ${times}$ $10^5$, and threshold voltage of 0 V. The straightly defined atomic force microscopy (AFM) images of channel area demonstrated that shadow effects caused by the S/D electrode deposition were negligible. The fabricated pentacene TFTs have an average channel length of 5 ${\pm}$ 0.25 ${\mu}m$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.165-168
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• 2000

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color fiat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. In addition, PDAST can estimate voltage distributions in common electrode which can affect pixel voltage and feed-through voltage. Since PDAST can simulate the gate, data and the pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of common electrode voltage can be effectively analyzed. The information obtained from this study could be utilized to design the larger area and finer image quality panel.