• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.3
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• pp.329-336
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• 2000

An important problem associated with adaptive sidelobe canceller(SLC) systems is that their performance deteriorates with an increase in jammers arriving from different directions. Generally the number of jammers which can be effectively cancelled is limited by the number of the auxiliary elements in a SLC system. But the single-auxiliary-element with tapped delay line adaptive filter can effectively cancel multiple jammers. Therefore this paper proposed the spatio-temporal processing structure cascading adaptive array and tapped delay line adaptive filter and showed that this could obtain more rapid convergence rate and an increase of DOF without increasing the number of element.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.28-40
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• 2007

In this paper, we proposes an idea for improved sound characteristic which decreasing a problem in previous reverberation algorism structure. To later reflection sound, proposed new reverberation structure, using a lopped and nested all-pass delay line, and it is designed to improve an natural concert hall sound. In addition, In order to have best imaginary sound effect, we extracted the factors by controlling each delay line's delay time, and we realized a proposed new algorithm by using general-purpose DSP. Through several experimental cases, we observed better effect on improvement of linear flatten and reverberation density and decreasing about colorlessness and non-linear sound at previous proposed model about impulse input.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• International Journal of Internet, Broadcasting and Communication
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• v.4 no.1
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• pp.18-22
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• 2012

In this paper, we propose an equivalent Wiener-Hopf equation. The proposed algorithm can obtain the weight vector of a TDL(tapped-delay-line) filter and the error simultaneously if the inputs are orthogonal to each other. The equivalent Wiener-Hopf equation was analyzed theoretically based on the MMSE(minimum mean square error) method. The results present that the proposed algorithm is equivalent to original Wiener-Hopf equation. In conclusion, our method can find the coefficient of the TDL (tapped-delay-line) filter where a lattice filter is used, and also when the process of Gram-Schmidt orthogonalization is used. Furthermore, a new cost function is suggested which may facilitate research in the adaptive signal processing area.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.500-504
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• 2011

In this paper, we propose an equivalent Wiener-Hopf equation. The proposed algorithm can obtain the weight vector of a TDL(tapped-delay-line) filter and the error simultaneously if the inputs are orthogonal to each other. The equivalent Wiener-Hopf equation was analyzed theoretically based on the MMSE(minimum mean square error) method. The results present that the proposed algorithm is equivalent to original Wiener-Hopf equation. The new algorithm was applied into the identification of an unknown system for evaluating the performance of the proposed method. We compared the Wiener-Hopf solution with the equivalent Wiener-Hopf solution. The simulation results were similar to those obtained in the theoretical analysis. In conclusion, our method can find the coefficient of the TDL (tapped-delay-line) filter where a lattice filter is used, and also when the process of Gram-Schmidt orthogonalization is used. Furthermore, a new cost function is suggested which may facilitate research in the adaptive signal processing area.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.160-166
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• 1989

We propose adaptive algorithms computing the coefficients of spatial domain predictors. The method uses the LMS approach to compute the coefficients of the predictors realized by using the TDL(tapped-delay-line) and the ESC (escalator) structures. The predictors to be presented differ from the conventional ones in the sense that the relevant weights are updated such that the sum of the mean squared values of the forward and the backward prediction errors is minimized. Using the coefficients of such spatial domain predictors yields improved linear predictive spatial spectrums. The algorithms are applied to the problems of estimating incident angles of multiple narrow-band signals received by a linear array of sensors. Simulation results demonstrating the performances of the proposed methods are presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.245-249
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• 2011

In this paper, we propose an equivalent Wiener-Hopf equation. The proposed algorithm can obtain the weight vector of a TDL(tapped-delay-line) filter and the error simultaneously if the inputs are orthogonal to each other. The equivalent Wiener-Hopf equation was analyzed theoretically based on the MMSE(minimum mean square error) method. The results present that the proposed algorithm is equivalent to original Wiener-Hopf equation. In conclusion, our method can find the coefficient of the TDL (tapped-delay-line) filter where a lattice filter is used, and also when the process of Gram-Schmidt orthogonalization is used. Furthermore, a new cost function is suggested which may facilitate research in the adaptive signal processing area.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.