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http://dx.doi.org/10.5573/ieie.2014.51.8.156

Time-to-Digital Converter Implemented in Field-Programmable Gate Array using a Multiphase Clock and Double State Measurements  

Jung, Hyun-Chul (Department of Radio Science and Engineering, Kwangwoon University)
Lim, Hansang (Department of Electronics Convergence Engineering, Kwangwoon University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.8, 2014 , pp. 156-164 More about this Journal
Abstract
In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.
Keywords
TDC; FPGA; Tapped delay line; Multiphase clock; State machine;
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