Nuclear Engineering and Technology

Korean Nuclear Society (한국원자력학회)
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Linearity improvement of UltraScale+ FPGA-based time-to-digital converter

  • Jaewon Kim (Department of Electronic Engineering, Sogang University) ;
  • Jin Ho Jung (Department of Electronic Engineering, Sogang University) ;
  • Yong Choi (Department of Electronic Engineering, Sogang University) ;
  • Jiwoong Jung (Department of Electronic Engineering, Sogang University) ;
  • Sangwon Lee (Department of Electronic Engineering, Sogang University)
  • Received : 2022.05.03
  • Accepted : 2022.10.11
  • Published : 2023.02.25
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Abstract

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

Keywords

Acknowledgement

This research was supported by the Korea Medical Device Development Fund grant funded by the Korea government (the Ministry of Science and ICT, the Ministry of Trade, Industry and Energy, the Ministry of Health & Welfare, the Ministry of Food and Drug Safety) (No. RS-2020-KD000006/1711137869 and RS-2020-KD000017/1711137911) and by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (No. 2019R1I1A1A01051112).

References

  1. B.K. Swann, B. Blalock, L.G. Clonts, D. Binkley, J.M. Rochelle, E. Breeding, K.M. Baldwin, A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications, IEEE J. Solid State Circ. 39 (2004) 1839-1852. https://doi.org/10.1109/JSSC.2004.835832
  2. A.S. Yousif, J.W. Haslett, A fine resolution TDC architecture for next generation PET imaging, IEEE Trans. Nucl. Sci. 54 (2007) 1574-1582. https://doi.org/10.1109/TNS.2007.903183
  3. G. Sportelli, N. Belcari, P. Guerra, F. Spinella, G. Franchi, F. Attanasi, S. Moehrs, V. Rosso, A. Santos, A. Del Guerra, Reprogrammable acquisition architecture for dedicated positron emission tomography, IEEE Trans. Nucl. Sci. 58 (2011) 695-702. https://doi.org/10.1109/TNS.2011.2113193
  4. J.Y. Won, J.S. Lee, Highly integrated FPGA-only signal digitization method using single-ended memory interface input receivers for time-of-flight PET detectors, IEEE Trans. Biomed. Circuits Syst. 12 (2018) 1401-1409. https://doi.org/10.1109/TBCAS.2018.2865581
  5. E. Venialgo, N. Lusardi, F. Garzetti, Angelo Geraci, S. Brunner, D. Schaart, E. Charbon, Toward a full-flexible and fast-prototyping TOFPET block detector based on TDC-on-FPGA, IEEE Trans. Radiat. Plasma Med. Sci. 3 (2019) 538-548. https://doi.org/10.1109/TRPMS.2018.2874358
  6. D. Tyndall, B. Rae, Day-Uei Li, J. Arlt, A. Johnston, J. Richardson, R. Henderson, A high-throughput time-resolved mini-silicon photomultiplier with embedded fluorescence lifetime estimation in 0.13 mm CMOS, IEEE Trans. Biomed. Circuits Syst. 6 (2012) 562-570. https://doi.org/10.1109/TBCAS.2012.2222639
  7. H. Wang, Y. Yang, Z. Huang, H. Gui, Instrument for real-time measurement of low turbidity by using time-correlated single photon counting technique, IEEE Trans. Instrum. Meas. 64 (2015) 1075-1083. https://doi.org/10.1109/TIM.2014.2364703
  8. K. Maatta, J. Kostamovaara, A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications, IEEE Trans. Instrum. Meas. 47 (1998) 521-536. https://doi.org/10.1109/19.744201
  9. J.P. Jansson, V. Koskinen, A. Mantyniemi, J. Kostamovaara, A multichannel high-precision CMOS time-to-digital converter for laser-scanner-based perception systems, IEEE Trans. Instrum. Meas. 61 (2012) 2581-2590. https://doi.org/10.1109/TIM.2012.2190343
  10. C. Liu, Y. Wang, A 128-channel, 710 M samples/second, and less than 10 ps RMS resolution time-to-digital converter implemented in a kintex-7 FPGA, IEEE Trans. Nucl. Sci. 62 (2015) 773-783. https://doi.org/10.1109/TNS.2015.2421319
  11. J.Y. Won, J.S. Lee, Time-to-digital converter using a tuned-delay line evaluated in 28-, 40-, and 45-nm FPGAs, IEEE Trans. Instrum. Meas. 65 (2016) 1678-1689. https://doi.org/10.1109/TIM.2016.2534670
  12. J. Zheng, P. Cao, D. Jiang, Q. An, Low-cost FPGA TDC with high resolution and density, IEEE Trans. Nucl. Sci. 64 (2017) 1401-1408. https://doi.org/10.1109/TNS.2017.2705802
  13. H. Xia, G. Cao, N. Dong, A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA, Rev. Sci. Instrum. 90 (2019).
  14. Y. Wang, C. Liu, A 3.9 ps time-interval RMS precision time-to-digital converter using a dual-sampling method in an UltraScale FPGA, IEEE Trans. Nucl. Sci. 63 (2016) 2617-2621. https://doi.org/10.1109/TNS.2016.2596305
  15. Y. Wang, C. Liu, A 4.2 ps time-interval RMS resolution time-to-digital converter using a bin decimation method in an UltraScale FPGA, IEEE Trans. Nucl. Sci. 63 (2016) 2632-2638. https://doi.org/10.1109/TNS.2016.2606627
  16. N. Lusardi, F. Garzetti, N. Corna, R. De Marco, A. Geraci, Very high-performance 24-channels time-to-digital converter in Xilinx 20-nm kintex UltraScale FPGA, in: IEEE Nuclear Science Symposium (NSS) and Medical Imaging Conference (MIC), Manchester, UK, October 26 - November 2, 2019.
  17. Y. Wang, Q. Cao, A multi-chain merged tapped delay line for high precision time-to-digital converters in FPGAs, IEEE Trans. Circuits Syst. II-Express Briefs 65 (2018) 96-100.
  18. M.W. Fishburn, L.H. Menninga, C. Favi, E. Charbon, A 19.6 ps, FPGA-based TDC with multiple channels for open source applications, IEEE Trans. Nucl. Sci. 60 (2013) 2203-2208. https://doi.org/10.1109/TNS.2013.2241789
  19. J. Torres, A. Aguilar, R. Garcia-Olcina, P.A. Martinez, J. Martos, J. Soret, J. Benlloch, P. Conde, A. Gonzalez, F. S anchez, Time-to-digital converter based on FPGA with multiple channel capability, IEEE Trans. Nucl. Sci. 61 (2014) 107-114. https://doi.org/10.1109/TNS.2013.2283196
  20. J.Y. Won, S.I. Kwon, H.S. Yoon, G.B. Ko, J.-W. Son, J.S. Lee, Dual-phase tapped-delay-line time-to-digital converter with on-the-fly calibration implemented in 40 nm FPGA, IEEE Trans. Biomed. Circuits Syst. 10 (2016) 231-242. https://doi.org/10.1109/TBCAS.2015.2389227
  21. J. Wu, Several key issues on implementing delay line based TDCs using FPGAs, IEEE Trans. Nucl. Sci. 57 (2010) 1543-1548. https://doi.org/10.1109/TNS.2010.2045901
  22. E. Bayer, M. Traxler, A high-resolution (< 10 ps RMS) 48-channel time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA), IEEE Trans. Nucl. Sci. 58 (2011) 1547-1552. https://doi.org/10.1109/TNS.2011.2141684
  23. X. Qin, L. Wang, D. Liu, Y. Zhao, X. Rong, J. Du, A 1.15-ps bin size and 3.5-ps single-shot precision time-to-digital converter with on-board offset correction in an FPGA, IEEE Trans. Nucl. Sci. 64 (2017) 2951-2957. https://doi.org/10.1109/TNS.2017.2768082
  24. C. Herve, J. Cerrai, T. Le Ca er, High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations, Nucl. Instrum. Methods Phys. Res. 682 (2012) 16-25. https://doi.org/10.1016/j.nima.2012.04.040
  25. F. Garzetti, N. Corna, N. Lusardi, A. Geraci, Time-to-digital converter IP-core for FPGA at state of the art, IEEE Access 9 (2021) 85515-85528. https://doi.org/10.1109/ACCESS.2021.3088448
  26. Y. Wang, J. Kuang, C. Liu, Q. Cao, A 3.9-ps RMS precision time-to-digital converter using ones-counter encoding scheme in a kintex-7 FPGA, IEEE Trans. Nucl. Sci. 64 (2017) 2713-2718. https://doi.org/10.1109/TNS.2017.2746626
  27. M.-A. Daigneault, J.P. David, A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA, in: IEEE International NEWCAS Conference, Montreal, QC, Canada, June 20-23, 2010.
  28. D. Chaberski, Time-to-digital-converter based on multiple-tapped-delay-line, Measurement 89 (2016) 87-96. https://doi.org/10.1016/j.measurement.2016.03.065
  29. N. Lusardi, F. Garzetti, A. Geraci, The role of sub-interpolation for delay-line time-to-digital converters in FPGA devices, Nucl. Instrum. Methods Phys. Res. 916 (2019) 204-214. https://doi.org/10.1016/j.nima.2018.11.100
  30. S. Surti, J.S. Karp, Update on latest advances in time-of-flight PET, Phys. Med. 80 (2020) 251-258. https://doi.org/10.1016/j.ejmp.2020.10.031