• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.108.1-108.1
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• 2014

제품의 고성능 사양을 위해 초미소 크기(Nano Size)의 구조를 갖는 제품들이 일상에서 자주 등장한다. 대표 제품은 주변에서 쉽게 접할 수 있는 전자제품의 반도체 칩이다. 반도체 칩 소자 구조는 크기를 줄이는 것 외에도 적층을 통해 소자의 집적도를 높이는 방향으로 진화를 하고 있다. 복잡한 구조로 인해 발생되는 여러 반도체 결함 중에 TSV 결함은 현재 진화하는 반도체 칩의 구조를 대변하는 대표 결함이다. 이 결함을 효율적으로 검출하고 다루기 위해서는 초미소 크기(Nano Size)의 결함을 비파괴적인 방법으로 가시화하고 분석하는 장비가 필요하다. X-ray 시스템은 이러한 요구를 해결하는 훌룡한 한 방법이다. 이 논문에서는 X-ray 시스템의 구성 및 위의 TSV 결함을 검출하고 분석하기 위한 시스템의 특징에 대해 설명을 한다. X-ray 시스템은 크게 X선을 발생시키는 X선튜브와 대상 물체를 투과한 X선을 영상화하는 디텍터, 대상물체의 영상화를 위해 물체를 적절하게 구동시키는 이동장치로 구성되어 있다. 초미소크기(Nano Size)의 결함 검출을 위해서는 X선 튜브, 디텍터, 이동장치에 요구되는 사양의 복잡도, 정밀도는 이러한 시스템의 개발을 어렵게 만든다. 이 논문에서는 이러한 시스템을 개발 시에 시스템 핵심 요소의 특징을 분석한다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.80-80
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• 2018

실리콘 관통전극 (Through Silicon Via, TSV)는 메모리 칩을 적층하여 고밀도의 집적회로를 구현하는 기술로, 기존의 와이어 본딩 (Wire bonding) 기술보다 낮은 소비전력과 빠른 속도가 특징인 3차원 집적기술 중 하나이다. TSV는 일반적으로 도금 공정을 통하여 충전되는데, 고종횡비의 TSV에 결함 없이 구리를 충전하기 위해서 3종의 유기첨가제(억제제, 가속제, 평탄제)가 도금액에 첨가되어야 한다. 이러한 첨가제 중 결함 발생유무에 가장 큰 영향을 주는 첨가제는 평탄제이기 때문에, 본 연구에서는 이미다졸(imidazole) 계열, 이민(imine) 계열, 디아조늄(diazonium) 계열 및 피롤리돈(pyrrolidone) 계열과 같은 평탄제(leveler)의 작용기에 따라 TSV 충전 성능을 조사하였다. TSV 충전 시 관능기의 거동을 규명하기 위해 QCM (quartz crystal microbalance) 및 EQCM (electrochemical QCM)을 사용하여 흡착 정도를 측정하였다. 실험 결과, 디아조늄 계열의 평탄제는 TSV를 결함 없이 충전하였지만 다른 작용기를 갖는 평탄제는 TSV 내 결함이 발생하였다. QCM 분석에서 디아조늄 계열의 평탄제는 낮은 흡착률을 보이지만 EQCM 분석에서는 높은 흡착률을 나타내었다. 즉, 디아조늄 계열의 평탄제는 전기 도금 동안 전류밀도가 집중되는 TSV의 상부 모서리에서 국부적인 흡착을 선호하며 이로 인하여 무결함 충전이 달성된다고 추론할 수 있다.

• Korean Chemical Engineering Research
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• v.54 no.6
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• pp.723-733
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• 2016

Intensive researches have been focused on the 3-dimensional packaging technology using through silicon via (TSV) to overcome the limitation in Cu interconnection scaling. Void-free filling of TSV by the Cu electrodeposition is required for the fabrication of reliable electronic devices. It is generally known that sufficient inhibition on the top and the sidewall of TSV, accompanying the selective Cu deposition on the bottom, enables the void-free bottom-up filling. Organic additives contained in the electrolyte locally determine the deposition rate of Cu inside the TSV. Investigation on the additive chemistry is essential for understanding the filling mechanisms of TSV based on the effects of additives in the Cu electrodeposition process. In this review, we introduce various filling mechanisms suggested by analyzing the additives effect, research on the three-additive system containing new levelers synthesized to increase efficiency of the filling process, and methods to improve the filling performance by modifying the functional groups of the additives or deposition mode.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.343-343
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• 2015

고종횡비의 실리콘 관통전극(TSV)은 반도체 3차원 적층을 실현하기 위한 핵심적인 기술이다. TSV의 충전은 주로 전해도금을 이용하는데 무결함 충전을 위해서 도금액에 몇 가지 첨가제(억제제, 가속제, 평탄제)가 포함된다. 본 연구에서는 첨가제 유무 따른 비아 충전 양상 및 무결함 충전에 대한 연구를 진행하였다. 비아 충전 공정을 위해서 직경 10 um, 깊이 50 um의 TSV가 패터닝된 웨이퍼를 준비하였으며 도금 후 단면을 관찰하여 도금의 양상을 비교하였다. 도금액에 첨가제가 포함되지 않는 조건, 억제제와 가속제만 포함된 조건, 세 가지 첨가제가 모두 포함된 조건으로 비아 충전을 실행하였으며 최종적으로 무결함 충전이 되는 첨가제 조건을 찾을 수 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.23-29
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• 2010

This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.55-59
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• 2012

Defects such as voids or seams are frequently found in TSV via filling process. To achieve defect-free copper via filling, organic additives such as suppressor, accelerator and leveler were necessary in a copper plating bath. However, by-products stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this research, the effects of levelers on copper electrodeposition were investigated without suppressor and accelerator to lower the concentration of additives. Threelevelers(janus green B, methylene violet, diazine black) were investigated to study the effects of levelers on copper deposition. Electrochemical behaviors of these levelers were different in terms of deposition rate. Filling performances were analyzed by cross sectional images and its characteristics were different with variations of levelers.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.3
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• pp.200-205
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• 2015

An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.