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Three-Dimensional Stacked Memory System for Defect Tolerance  

Han, Se-hwan (Department of Electronics Engineering, Chungbuk National University)
You, Young-Gap (Department of Information and Communication Engineering, Chungbuk National University)
Cho, Tae-Won (Department of Electronics Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.11, 2010 , pp. 23-29 More about this Journal
Abstract
This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.
Keywords
Defect tolerance; memory stacking; TSV; independently addressable block; spare chips;
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