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http://dx.doi.org/10.5370/KIEE.2014.63.12.1710

TSV Defect Detection Method Using On-Chip Testing Logics  

Ahn, Jin-Ho (Dept. of Electronic Engineering, Hoseo University)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.63, no.12, 2014 , pp. 1710-1715 More about this Journal
Abstract
In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.
Keywords
TSV test; On-chip test logic; Pre-bond test; Post-bond test; 3D-IC;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
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