• Title/Summary/Keyword: T-gate

Search Result 460, Processing Time 0.036 seconds

A Study on Switching Characteristics of 1,200V Trench Gate Field stop IGBT Process Variables (1,200V 급 Trench Gate Field stop IGBT 공정변수에 따른 스위칭 특성 연구)

  • Jo, Chang Hyeon;Kim, Dea Hee;Ahn, Byoung Sup;Kang, Ey Goo
    • Journal of IKEEE
    • /
    • v.25 no.2
    • /
    • pp.350-355
    • /
    • 2021
  • IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low VCE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, VCE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

A study on electron beam lithography for 0.1$\mu\textrm{M}$ T-gate formation at P(MMA/MAA)/PMMA structure (PMMA/P(MMA/MAA) 구조에서 0.1$\mu\textrm{M}$ T-gate 형성을 위한 전자빔 리소그래피 공정에 관한 연구)

  • Choe, Sang-Su;Lee, Jin-Hui;Yu, Hyeong-Jun;Lee, Sang-Yun
    • Korean Journal of Materials Research
    • /
    • v.5 no.1
    • /
    • pp.96-103
    • /
    • 1995
  • This art~cle reports on the formation of T - Gate with O.1$\mu$m foot and 0.4$\mu$m head width at PMMA/P( MMA/MAA) resist structure using a 30KV electron beam lithography system. From the result of Monte Carlo simulation on PMMA/P( MMA/MAA)/GaAs, we obtain the dissipation energy ratio of forwardscattered electron and backscattered electron within 0.1$\mu$m scattering radius is 19.5 : 1 0.1$\mu$m T - gate has been formed with 30KV gaussian electron beam at a 440$\mu C/\textrm{cm}^2$ dosage. The gamma value of PMMA and P(MMA/MAA) at MIBK : IPA=l : 1 developer was 2.3. The overlay accuracy(3$\sigma$) from mix-andmatch of optical stepper and Ekeam lithography system for fabricating HEMT device is accomplished below 0.1$\mu$m.

  • PDF

Analyses for RF parameters of Tunneling FETs (터널링 전계효과 트랜지스터의 고주파 파라미터 추출과 분석)

  • Kang, In-Man
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.4
    • /
    • pp.1-6
    • /
    • 2012
  • This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

A New Active Gate Drive Circuit for High Power IGBTs (대용량 IGBT를 위한 새로운 능동 게이트 구동회로)

  • 서범석;현동석
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.4 no.2
    • /
    • pp.111-121
    • /
    • 1999
  • This paper deals with an active gate drive (AGD) technolo밍T for high power IGBTs. It is based on an optimal c combination of several requirements necessmy for good switching performance under hard switching conditions, The s scheme specifically combines together the slow drive requirements for low noise and switching stress and the fast driver requirements for high speed switching and low switching energy loss The gate drive can also effectively dampen oscillations during low cunent turnlongrightarrowon transient in the IGBT, This paper looks at the conflicting requirements of the c conventional gate dlive circuit design and the experimental results show that the proposed threelongleftarrowstage active gate dlive t technique can be an effective solution.

  • PDF

Analysis of The Electrical Characteristics of Power IGBT According to Design and Process Parameter (설계 및 공정 변수에 따른 600 V급 IGBT의 전기적 특성 분석)

  • Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.29 no.5
    • /
    • pp.263-267
    • /
    • 2016
  • In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

Electrical Characteristics of the Triac according to the Gate Diffusion Time (게이트 확산 시간에 따른 트라이액의 전기적 특성 연구)

  • Hong, N.P.;Choi, D.J.;Lee, T.S.;Choi, B.H.;Kim, T.H.;Hong, J.W.
    • Proceedings of the KIEE Conference
    • /
    • 2002.07c
    • /
    • pp.1606-1608
    • /
    • 2002
  • The triac is a bidirectional triode with blocking and conducting characteristics used in motor control or heater power control. This greatly simplifies the circuits required for the control of the full wave AC Power by reducing the number of power handling components and by reducing the size and complexity of the gate control circuit.[3] In this paper, We can understand measurement results of analysis which have been made on the electrical characteristics of triac with gate diffusion time for the gate area.

  • PDF

A Comparative Study of a Dielectric-Defined Process on AlGaAs/InGaAs/GaAs PHEMTs

  • Lim, Jong-Won;Ahn, Ho-Kyun;Ji, Hong-Gu;Chang, Woo-Jin;Mun, Jae-Kyoung;Kim, Hae-Cheon;Cho, Kyoung-Ik
    • ETRI Journal
    • /
    • v.27 no.3
    • /
    • pp.304-311
    • /
    • 2005
  • We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

  • PDF

Fabrication of $0.25 \mu\textrm{m}$ P-HEMT for X-band Low Noise Amplifier (X-밴드 저잡음 증폭기용 $0.25 \mu\textrm{m}$ T-형 게이트 P-HEMT 제작)

  • 이강승;정윤하
    • Proceedings of the IEEK Conference
    • /
    • 2000.11b
    • /
    • pp.17-20
    • /
    • 2000
  • We have enhanced the yield of 0.25 ${\mu}{\textrm}{m}$ T-gate $Al_{0.25}$G $a_{0.75}$As/I $n_{0.2}$G $a_{0.8}$As P-HEMT using three-layer E-beam lithography process and selective etching process. The three-layer resist structure (PMMA/copolymer/ PMMA=2000 $\AA$/3000 $\AA$/2000 $\AA$) and three developers (Benzene:IPA=1:1,Methanol:IPA =1:1,MIBK:IPA=1:3) were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. Also 1 wt% citric acid: $H_2O$$_2$:N $H_{4}$OH(200m1:4ml:2.2ml) solution were used for uniform gate recess. The etching selectivity of GaAs over $Al_{0.25}$G $a_{0.75}$As is measured to be 80. So these P-HEMT processes can be used in X-band MMIC LNA fabrication.ion.ion.ion.

  • PDF

Optimization of 70nm nMOSFET Performance using gate layout (게이트 레이아웃을 이용한 70nm nMOSFET 초고주파 성능 최적화)

  • Hong, Seung-Ho;Park, Min-Sang;Jung, Sung-Woo;Kang, Hee-Sung;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.581-582
    • /
    • 2006
  • In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

  • PDF