• Journal of the Korean Society of Safety
• /
• v.16 no.2
• /
• pp.22-26
• /
• 2001

The machining process on be considered as a planned interaction of the workpiece, the tool and the machine tool. In an unmanned situation, the results of this interaction are to be continuously monitored so that any changes in the machining environment on be sensed to corrective actions. In order to design the process monitoring system for unmanned manufacturing, the identification of chip formation is proposed. The system proposes the method of using acoustic emission(AE) signal analysis to identify the chip formation during cutting.

• Nuclear Engineering and Technology
• /
• v.55 no.3
• /
• pp.1015-1020
• /
• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

• Electronics and Telecommunications Trends
• /
• v.24 no.6
• /
• pp.86-93
• /
• 2009

프로세서는 더 이상 동작 주파수를 높이는 방법이 아닌 다수의 프로세서를 집적하는 멀티프로세서로 기술 발전이 이루어지고 있다. 최근 2, 4, 8개의 프로세서 코어를 넘어 64, 128개 이상의 프로세서를 집적한 대규모 데이터 처리 및 과학 연산용 고성능 프로세서들이 개발되고 있다. 본 문서는 이러한 병렬 프로세싱의 개념 및 병렬 프로세서의 기술을 정리하고 최근 동향과 함께 당면한 문제점들을 기술한다.

• The Magazine of the IEIE
• /
• v.29 no.1
• /
• pp.66-72
• /
• 2002

VLSI 기술의 발전은 보다 많은 양의 로직을 단일 칩에 집적 가능하게 했고, 이는 System-on-a-chip 시대의 도래를 가능하게 했다. System-on-a-chip을 가능하게 하기 위해서는 많은 종류의 IP (Intellectual Property)가 필요하고, 공정 변환을 쉽게 하기 위해서는 합성이 가능한 RTL 설계가 절실히 요구된다. 본 논문은 이러한 요구에 부응하기 위해서 hard macro 형태의 기존의 IP로 부터 합성 가능한 IP를 자동 생성해 주는 ART(Automatic RTL Translation)로 명명된 기법에 관한 것이다. 제안된 ART 기법을 이용하여 80C52 호환의 8-bit MCU(Micro-controller Unit)의 합성 가능한 RTL model을 자동 생성하였고, 개발된 Soft IP를 이용하여 TCP/IP 전용 MCU를 표함해서 다양한 제품들을 개발하였다.

• Journal of the Semiconductor & Display Technology
• /
• v.1 no.1
• /
• pp.29-33
• /
• 2002

In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

• Design & Manufacturing
• /
• v.6 no.2
• /
• pp.74-78
• /
• 2012

A multi-cavity injection mold system of protein chip for point-of-care with cavity temperature and pressure sensors was proposed in this work. In advance of manufacturing for the multi-cavity injection mold system, a single cavity injection mold system to mold protein chip was considered. Injection molding analysis for the presented system was performed to optimize the process of the molding and suggest guides to design. On the basis of the results for the single cavity system, a multi-cavity injection mold system for protein chip was analyzed, designed and manufactured with cavity temperature and pressure sensors. Results of balanced filling for protein chip models were obtained from the presented mold system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.198-206
• /
• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.12
• /
• pp.1045-1054
• /
• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Molecules and Cells
• /
• v.27 no.3
• /
• pp.337-343
• /
• 2009

We developed a novel on-chip activity assay using protein arrays for quantitative and rapid analysis of transglutaminase activity in mammalian cells. Transglutaminases are a family of $Ca^{2+}$-dependent enzymes involved in cell regulation as well as human diseases such as neurodegenerative disorders, inflammatory diseases and tumor progression. We fabricated the protein arrays by immobilizing N,N'-dimethylcasein (a substrate) on the amine surface of the arrays. We initiated transamidating reaction on the protein arrays and determined the transglutaminase activity by analyzing the fluorescence intensity of biotinylated casein. The on-chip transglutaminase activity assay was proved to be much more sensitive than the $[^3H]putrescine$-incorporation assay. We successfully applied the on-chip assay to a rapid and quantitative analysis of the transglutaminase activity in all-trans retinoic acid-treated NIH 3T3 and SH-SY5Y cells. In addition, the on-chip transglutaminase activity assay was sufficiently sensitive to determine the transglutaminase activity in eleven mammalian cell lines. Thus, this novel on-chip transglutaminase activity assay was confirmed to be a sensitive and high-throughput approach to investigating the roles of transglutaminase in cellular signaling, and, moreover, it is likely to have a strong potential for monitoring human diseases.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.24-38
• /
• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.