• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.189-195
• /
• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1439-1444
• /
• 2005

Induction motors are the most commonly used electrical drives because they are rugged, mechanically simple, adaptable to widely different operating conditions, and simple to control. The most common faults in squirrel-cage induction motors are bearing, stator and rotor faults. Surveys conducted by the IEEE and EPRI show that the most common fault in induction motor is bearing failure (${\sim}$40% of failure). Thence, this paper addresses experimental results for diagnosing faults with different rolling element bearing damage via motor current spectral analysis. Rolling element bearings generally consist of two rings, an inner and outer, between which a set of balls or rollers rotate in raceways. We set the experimental test bed to detect the rolling-element bearing misalignment of 3 type induction motors with normal condition bearing system, shaft deflection system by external force and a hole drilled through the outer race of the shaft end bearing of the four pole test motor. This paper takes the initial step of investigating the efficacy of current monitoring for bearing fault detection by incipient bearing failure. The failure modes are reviewed and the characteristics of bearing frequency associated with the physical construction of the bearings are defined. The effects on the stator current spectrum are described and related frequencies are also determined. This is an important result in the formulation of a fault detection scheme that monitors the stator currents. We utilized the FFT, Wavelet analysis and averaging signal pattern by inner product tool to analyze stator current components. The test results clearly illustrate that the stator signature can be used to identify the presence of a bearing fault.

• Journal of KIISE:Computing Practices and Letters
• /
• v.14 no.5
• /
• pp.542-546
• /
• 2008

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.

• Journal of the Institute of Convergence Signal Processing
• /
• v.7 no.1
• /
• pp.17-23
• /
• 2006

In recent years, RFID has received much attention because of spread usage in industrial applications including factory, material flow, logistics and defense areas. However, there is only CRC-16 for error detection in ISO/IEC 18000-6 Protocols prepared for 860-960 MHz RFID, high error rates are expected in cases of high level of security and noisy envirionment. In this paper, we propose a usage of convolution code as a method for satisfying the high level of security requirement and system error performance.'1'he signal control function is implemented in a microprocessor with RF modulation and the convolutional encoding and Viterbi decoding are implemented in an FPGA chip.'The frame error rates are measured with and without convolution coding under the channel conditions of line-of- sight and non line-of-sight, respectively.

• Korean Journal of Optics and Photonics
• /
• v.16 no.4
• /
• pp.361-365
• /
• 2005

An absolute interferometer system with multiple point-sources is devised for tile 3-D measurement of rough surface profiles. The positions of the point sources are determined to be the system parameters that influence the measurement accuracy, so they are calibrated precisely prior to performing actual measurements. For the calibration, a CCD camera composed of a two-dimensional array of photo-detectors was used. Performing optimization of the cost function constructed with phase values measured at each pixel on the CCD camera, the position coordinates of each point source is precisely determined. Measurement results after calibration performed for the warpage inspection of chip scale packages (CSPs) demonstrate that the maximum discrepancy is 9.8 mm with a standard deviation o( 1.5 mm in comparison with the test results obtained by using a Form Taly Surf instrument.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.130-133
• /
• 2002

As a society advances, an aging phenomenon and many diseases which did not exist in old times are happening. Especially, in case of the aged patient, because we cant know the time the condition of the patients health become worse, the study of the Tele-information system has been actively carried out by the necessity of a persistent observation. A ECG signal a kind of a vital signals has been widely used to the medical information system as an usual clinical diagnosis for the patients who possess heart diseases. BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self - error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, It will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the small size is present According to this, Bluetooth module transmits the medical information, which is input from the outside among the operations that use the Bluetooth to the Bluetooth module that is connected the host PC. And the system that the host PC transmits the medical information from the connected Bluetooth module to the Internet has once embedded. this study let the host PC embedded in advance of the existing system and transmit the medical information by the addition of the Tcp/Ip protocol stark under all embedded environments to internet.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.60-68
• /
• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1A
• /
• pp.93-98
• /
• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Convergence Signal Processing
• /
• v.6 no.4
• /
• pp.206-211
• /
• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.11
• /
• pp.1470-1476
• /
• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.