• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.33-39
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• 2018

For the integration test in the current field of defense simulation, each actual equipment and simulator's logging information is automated. Although the event of the integrated test system is written in the test log, it is not automated, and relies on the operator's handwriting or file creation, resulting in ineffective aspects such as low-quality record content and repetition of the same content. In this study, we propose the automatic test report recording program that solves these problems. Automatic test report recording program uses framework-based technology to receive information from the test control computer and user to record a log of the test log. Automatic test report recording program allows the user to record the repeated test content in a stable manner. Additionally, even if the number of test operators is limited, the efficiency is improved so that we can fucus on the integration test.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Earthquakes and Structures
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• v.10 no.2
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• pp.367-388
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• 2016

Eccentrically braced frames (EBFs) represent an attractive lateral load resisting steel system to be used in areas of high seismicity. In order to assess the likely damage for a given intensity of ground shaking, fragility functions can be used to identify the probability of exceeding a certain damage limit-state, given a certain response of a structure. This paper focuses on developing a set of fragility functions for EBF structures, considering that damage can be directly linked to the interstorey drift demand at each storey. This is done by performing a Monte Carlo Simulation of an analytical expression for the drift capacity of an EBF, where each term of the expression relies on either experimental testing results or mechanics-based reasoning. The analysis provides a set of fragility functions that can be used for three damage limit-states: concrete slab repair, damage requiring heat straightening of the link and damage requiring link replacement. Depending on the level of detail known about the EBF structure, in terms of its link section size, link length and storey number within a structure, the resulting fragility function can be refined and its associated dispersion reduced. This is done by using an analytical expression to estimate the median value of interstorey drift, which can be used in conjunction with an informed assumption of dispersion, or alternatively by using a MATLAB based tool that calculates the median and dispersion for each damage limit-state for a given set of user specified inputs about the EBF. However, a set of general fragility functions is also provided to enable quick assessment of the seismic performance of EBF structures at a regional scale.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.7
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• pp.500-504
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• 2009

A reliability of software is a type of nonfunctional requirement. Traditionally, a validation of the reliability is processed at the integration phase in software development life cycle. However, it increases the cost and the risk for the development. In this paper, we propose reliability analysis method based on mathematical analytic model at the architecture design phase of the development process as follows. First, we propose the software modeling methodology for reliability analysis using Hierarchical combined Queueing Petri Nets(HQPN). Second, we derive the Markov Reward Model from the HQPN based model. We apply our approach to the video conference system to verify the usefulness of our approach. Our approach supports quantitative evaluation of the reliability.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Journal of the Korean housing association
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• v.25 no.5
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• pp.83-91
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• 2014

The main purpose of this research is to understand how the problems, which existing letter-shape houses have, are solved in Unjoru which is one of the letter-shape houses. Furthermore, there is the secondary purpose which is to realize the architectural characteristics of Unjoru through the process from the composition of rooms and buildings to the method of structure and roof formation. This research was approached in terms of architectural design, and as the result, the problems of the existing letter-shape houses was resolved by literally converting the shape of outdoor space to 品-shape form. Moreover through the result, it was recognized that the 占-Shape plan was flexible in responding to the demand of the times, such as the order of precedency within men and women and each generation. In addition to the previous results, it was confirmed that the location of major rooms was also decided by considering the interrelationship with natural environment of surrounding area. Also, in the whole proportion of building's plan, each building, such as ㄷ-shape Anchae and big-sized and middle-sized Sarangchae having 丁-shape form, and major rooms in the each building have proportion system such as 1:1, 3:4, $1:\sqrt{2}$, and 3:5 as aesthetic numerical value. Finally, it was understood that the architectural intention had double-sided characters, one side was authority and dignity in the aspect of shape and another side was practicality in aspect of inner housing life.

• Journal of Engineering Education Research
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• v.21 no.1
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• pp.27-36
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• 2018

This study aims to deduce operational implication of R-WeSET program through women students in science & engineering and companies's perception and assessment on the basis of NCS key competency. The significant results are as follows. Firstly, companies and women students in science & engineering share a similar perception on importance of NCS key competencies. The programs should be reviewed and improved for women students who are truly aware of companies' needs. Secondly, the main areas of NCS key competency that are poor in companies' perception are 'positive thinking & drive', 'creativity & challenge spirit', 'communication skills' and 'problem-solving skills'. To enhance these weak skills, activating the actual programs such as "Convergence Design Camp", "Field Adaptability Improvement" and developing the new communication program are required. Lastly, most of women students have attained the satisfying result from "Field Competency Reinforcement Program". Especially, "Industry Field Training" shared the great progresses on all skills of key competency, hence why the progressive model should be developed in the future. This study figures out who's the right person for the 4th Industrial Revolution era, producing a meaningful result in order to change in the higher education system of women students and to grow human resources who will contribute to the community and company.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.2
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• pp.955-961
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• 2013

This study aimed for the scientific approach of Korean traditional house, so called Hanok, by analyses of structural elements and thermal environmental performance. Hanok is a very unique vernacular architectural style of the Middle East Asia that fits with climate conditions of the Korean Peninsular, designed to withstand high temperature and humidity in summer and cold and dry in winter seasons. In order to evaluate thermal environment of Hanok, its sectional structure such as floor, wall, roof structure and Ondol which is Korean traditional floor heating system, was built in 3D, as well as heat transfer mechanism of its composing elements was analyzed through 3 dimensional steady state analysis. The results of the thermal environmental performance of Hanok will be used as a basic datum of design guidelines for accomplishing ecologic housing fitted with local climate.