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http://dx.doi.org/10.20465/KIOTS.2020.6.1.097

Filed Programmable Logic Control and Test Pattern Generation for IoT Multiple Object switch Control  

Kim, Eung-Ju (Dept. of Semiconductor Design, Semiconductor Convergence Campus of Korea Polytechnics)
Jung, Ji-Hak (Dept. of Semiconductor & Display, Asan Campus of Korea Polytechnics)
Publication Information
Journal of Internet of Things and Convergence / v.6, no.1, 2020 , pp. 97-102 More about this Journal
Abstract
Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.
Keywords
Multi-Channel switch IC; IoT; ON-resistance; shift register; Serialized logic; latch; FPGA;
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  • Reference
1 T.Y.Shim, "A Design of IoT based Automatic Control System for Intelligent Smart Home Network," Proceedings of the Conference of the Korea Internet of Things Society, Vol.1, No.1 pp.21-26, Dec. 2015.
2 C.S.Shin and Y.H.Lee, "Analysis of User Head Motion for Motion Classifier of Motion Headset," Proceedings of the Conference of the Korea Internet of Things Society, Vol.2, No.2 pp.1-6, Dec. 2016.
3 J.H.Hong, S.H.Kim and K.H.Lee, "Design of video surveillance system using k-means clustering," Proceedings of the Conference of the Korea Internet of Things Society, Vol.3, No.2 pp.1-6, Sep. 2017.
4 K.Hosaka, S.Morishita, I.Mori, M.Kubota, and Y.Mita, "An Integrated CMOS-MEMS Probe having Two-Tips per Cantilever for Individual Contact Sensing and Kelvin Measurement with Two Cantilevers," IEEE International Conference Microelectronic Test Structures, pp.3-6, 2013.
5 A.Banuaji and H.K.Cha, "A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology," pp.604-608, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, Vol.61, No.8, August, 2014.   DOI
6 MICROCHIP, datasheet, HV2601/2701 Low Charge Injection, 16-Channel, High-Voltage Analog Switch, 2018.
7 M.Yamaji, K.Abe, T.Maiguma, H.Takahashi, and H.Sumida, "A novel 600V-LDMOS with HV-interconnection for HVIC on thick SOI," International Symposium on Power Semiconductor Devices, pp.101-104, 2010.
8 ALTERA, Usual Manual, DE2 Development and Education Board, 2017.
9 F. Yamashita, J. Aizawa and H. Honda, "A New Compact, Low On Resistance and High Off Isolation High Voltage Analog Switch IC Without Using High Voltage Power Supplies for Ultrasound Imaging System," Proceedings of the International Symposium on Power Semiconductor Devices and ICs(ISPSD), pp.415-418, 2016.
10 M. Jankowski, "High voltage Current controlled Analog Switches for Various Kinds of Application," 11th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics CADSM, pp.42-45, 2011.
11 T.Miyoshi, T.Tominari, Y.Hayashi and M.Yoshinaga, "Design of Novel 300-V Field-MOS FETs with Low ON-Resistance for Analog Switch Circuits," IEEE transaction on electron devices, Vol.60, No.1, pp.354-359, 2013.   DOI
12 H.Lang, J.Pfeiffer and J.Maguire, "Using on-chip test pattern compression for full scan SoC designs," Proceedings International Test Conference, pp.638-643, 2000.
13 S.Shimamoto, Y.Yanagida, S.Shirakawa, K.Miyakoshi, T.Imai, T.Oshima, J.Sakano, and S.Wada, "High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology," IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, pp.44-47, 2011.
14 R.K.Williams, M.N.Darwish, R.A.Blanchard, R. Siemieniec, P. R. and Y. Kawaguchi, "The Trench Power MOSFET-Part II: Application Specific VDMOS, LDMOS, Packaging, and Reliability," IEEE Transactions on Electron Devices, Vol.64, pp.692-712, 2017.   DOI
15 M.Teramoto and T.Fukazawa, "Test pattern generation for circuits with asynchronous signals based on scan," Proceedings International Test Conference, pp.21-28, 1996.
16 M.Engelene, J.Obien, S.Ohtake and H.Fujiwara, "F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG," Sixteenth IEEE European Test Symposium, p.203, 2011.
17 H.E.Karrer, J.F.Dias, J.D.Larson, R.D.Pering, S.H.Maslak and D.A.Wilson, "A Phased Array Acoustic Imaging System for Medical Use," IEEE Ultrasonics Symposium, coustical Imaging Volume 10 of the series Acoustical Imaging, pp.47-639, 1980.
18 P.N.V.M.Sastry and D.N.Rao, "HDL Design For 20 Tbps Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card Design," Fifth International Conference on Communication Systems and Network Technologies, pp.844-847, 2015.