• Journal of Power Electronics
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• 제19권2호
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• pp.353-362
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• 2019

To address the problem of circulating current loss in the traditional zero-current switching (ZCS) full-bridge (FB) DC/DC converter, a ZCS FB DC/DC converter topology and modulation strategy is proposed in this paper. The strategy can achieve ZCS turn on and zero-voltage and zero-current switching (ZVZCS) turn off for the primary switches and realize ZVZCS turn on and zero-voltage switching (ZVS) turn off for the auxiliary switches. Moreover, its resonant circuit power is small. Compared with the traditional phase shift full-bridge converter, the new converter decreases circulating current loss and does not increase the current stress of the primary switches and the voltage stress of the rectifier diodes. The diodes turn off naturally when the current decreases to zero. Thus, neither reverse recovery current nor loss on diodes occurs. In this paper, we analyzed the operating principle, steady-state characteristics and soft-switching conditions and range of the converter in detail. A 740 V/1 kW, 100 kHz experimental prototype was established, verifying the effectiveness of the converter through experimental results.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.442-445
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• 1997

A challenging activity in the manufacturing industry is to perform in real time the continuous monitoring of the process state, the situation assessment and identification of the problem on line and diagnosis of the cause and importance of the problem if he process does not work properly. This paper describes LAT(Ladder Analysis Tool) system for fault tree generation to improving the fault diagnosis of CNC machine tools. The system consists of 4 steps which can automatically ladder analysis from ladder diagram to two diagnosis function models. The two diagnostic models based on he ladder diagram is switching function model and step switching function model. This system tries to overcome diagnosis deficiencies present machine tool.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.216-222
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• 2003

Today we have excellent motor drive system using high frequency carrier PWM control voltage source inverter in the other hand, we have met serious problems caused by high frequency switching. PWM Cyclo-converter called Matrix converter is expected as the new strategy Possible to improve these problems and add some more convenient features suitable for new drive system. in this Paper, we will introduce the background, features and outline of this converter, and additionally introduce some remarkable activity on this converter

• 전기학회논문지
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• 제60권5호
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• pp.1043-1048
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• 2011

Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• 제어로봇시스템학회논문지
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• 제20권3호
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• pp.333-344
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• 2014

This is the survey paper on the role of kinematics in robot development. The robot is considered as a form of mechanical systems which includes closed-chain loop system, open-chain loop system and closed and open switching system. To analyze these systems, kinematic notations has been developed in kinematics of mechanical theory since 1955 and has been applied in robotics. Several kinematic notations including Denavit-Hartenberg notations have been reviewed. The status of development of the spherical motor which has a great impact on the future robot advancement has reviewed, and research activity on a spherical motor and its application to 3-D spatial mechanisms at UNIST is introduced. For the open and closed switching mechanical systems, the bipedal robots' walking theories using Zero Moment Point are reviewed. And current status regarding bipedal robots based on newly developed passive dynamic walking theory is reviewed with the research activity at UNIST on this subject.

• Bulletin of the Korean Chemical Society
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• 제30권9호
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• pp.2138-2140
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• 2009

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 정보처리학회논문지A
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• 제8A권3호
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• pp.279-286
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• 2001

본 논문은 상위 레벨 합성 과정에서 DSP와 같은 회로를 대상으로 전력소모를 최소로 하는 스케줄링 및 자원할당 알고리즘을 제안한다. 본 논문에서는 스케줄링 시의 저 전력 설계는 리스트 스케줄링 방법을 이용한다. 그리고 자원공유를 통하여 자원할당 시 입력을 재 사용할 수 있는 가능성을 증가시킨다. 스케줄링 후 자원할당 방법은 두 입력 사이의 평균 해밍 거리와 교환동작을 계산한 결과값을 고려하여 전력 함수를 이용한다. 먼저 두 연산자 사이의 평균 해밍 거리를 계산한 후 입력 값에 대한 교환동작을 구하며, 입력 값의 비트 패턴을 이용하여 전력 값을 구한다. 자원 할당 과정은 제어 단계를 한 단계 씩 증가시키면서 각 제어 단계에서 할당 될 수 있는 모든 경우들에 대하여 평균 해밍 거리가 가장 적고 전력 함수에 의한 전력이 가장 적게 소비되는 연산자를 할당한다. 기존 방법과 비교했을 때 그 수행속도는 사용하는 연산자의 개수와 최다 제어 단계에 따라서 빨라진다. 그리고 소모하는 전력이 6%에서 8%까지 감소효과가 있었다.

• 한국융합학회논문지
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• 제11권4호
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• pp.143-149
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• 2020

많은 사람들이 위치 기반 증강현실 게임인 포켓몬 고를 즐기고 있다. 본 연구는 애착의 관점에서 포켓몬 고의사용에 대해 분석한다. 온라인 설문 방식을 통해 총 182명의 포켓몬 고 사용자의 자료가 수집되었다. 회귀분석 결과, 캐릭터에 대한 태도, 대인 교류, 경쟁심, 신체 활동은 게임 애착을 증가시켰고, 주의 전환은 게임 애착을 감소시켰다. 연구 결과는 위치 기반 증강현실 게임 설계 및 운영에 있어서 원천 캐릭터의 중요성, 게임에 반영된 대인 교류와 경쟁심이라는 사회적 상호작용 요소, 신체 활동의 증가라는 혜택이 애착을 증가시키는 요소임을 제시한다. 또한, 사용자의 주의 전환은 게임에 대한 애착을 감소시켰다. 본 연구는 모바일 증강현실 게임이 사회적 욕구와 신체 활동을 통한 건강증진이라는 혜택을 제공함으로써 사용자의 애착을 얻을 수 있음을 시사한다.