Browse > Article
http://dx.doi.org/10.5370/KIEE.2011.60.5.1043

A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout  

Lee, Jae-Hoon (여주대학 게임기획비즈니스과)
Baek, Chul-Ki (성균관대학교 정보통신공학부)
Kim, In-Soo (장안대학교 IT학부 인터넷정보통신과)
Min, Hyoung-Bok (성균관대학교 정보통신공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.60, no.5, 2011 , pp. 1043-1048 More about this Journal
Abstract
Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.
Keywords
Test vector; Power consumption; Fanout count; Vector reordering; Hamming distance;
Citations & Related Records

Times Cited By SCOPUS : 0
연도 인용수 순위
  • Reference
1 Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, "VLSI Test Principles and Architectures Design For Testability", Morgan Kaufmann Publishers, 2006
2 F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, "A Test Pattern Generation methodology for low power consumption", VLSI Test Symposium, 1998. Proceedings. 16th IEEE, pp. 453 - 457
3 P. Girard, C. Landraulault, S. Pravossoudovitch, D. Severac, "Reducing Power Consumption during Test Application by Test Vector Ordering", Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium, pp.296-299
4 P. Girard L. Guiller, C. Landraulault, S. Pravossoudovitch, "A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation", GLS '99 Proceedings of the ninth Lakes Symposium on VLSI , 1999
5 P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits", IEEE Transactions on Computers, vol. C-30, pp.676-683, March 1981
6 F. N. Najm,"Transition Density, a Stochastic Measure of Activity in Digital Circuits", ACM Design Automation Conference, pp. 655-649, June 1991
7 A. P. Chandrakasan, R. W. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers, 1995
8 Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba, "System on Chip Test Architectures Nanometer Design For Testability", Morgan Kaufmann Publishers, 2008
9 S. Wang, S. K. Gupta, "ATPG for Heat Dissipation Minimization During Test Application", International Test Conference 1994, pp 250-258
10 Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices", Proc. 11th IEEE VLSI Test Symposium, April 1993, pp. 4-9