• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1578-1581
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• 2009

This work describes a power and area efficient switched-capacitor cyclic DAC for mobile display drivers. The proposed DAC can be simply implemented with one opamp two capacitors and several switches. Furthermore, the op-amp input referred offset is attenuated at the DAC output without additional offset cancellation circuitry. The operation of the cyclic DAC is verified through circuit level simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.712-719
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• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.