• Title/Summary/Keyword: Switch design

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Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

  • Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Choi, JinWook;Park, SangHyeon;Kim, InSeong;Pu, YoungGun;Kim, JaeYoung;Hwang, Keum Cheol;Yang, Youngoo;Seo, Munkyo;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.126-142
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    • 2016
  • This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

Implementation of Front End Module for 2.4GHz WLAN Band (2.4GHz 무선랜 대역을 위한 Front End Module 구현)

  • Lee, Yun-Sang;Ryu, Jong-In;Kim, Dong-Su;Kim, Jun-Chul;Park, Jong-Dae;Kang, Nam-Kee
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.1
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    • pp.19-25
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    • 2008
  • In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

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A noble Sample-and-Hold Circuit using A Micro-Inductor To Improve The Contrast Resolution of X-ray CMOS Image Sensors (X-ray CMOS 영상 센서의 대조 해상도 향상을 위해 Micro-inductor를 적용한 새로운 Sample-and-Hold 회로)

  • Lee, Dae-Hee;Cho, Gyu-Seong;Kang, Dong-Uk;Kim, Myung-Soo;Cho, Min-Sik;Yoo, Hyun-Jun;Kim, Ye-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.4
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    • pp.7-14
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    • 2012
  • A image quality is limited by a sample-and-hold circuit of the X-ray CMOS image sensor even though simple mos switch or bootstrapped clock circuit are used to get high quality sampled signal. Because distortion of sampled signal is produced by the charge injection from sample-and-hold circuit even using bootstrapped. This paper presents the 3D micro-inductor design methode in the CMOS process. Using this methode, it is possible to increase the ENOB (effective number of bit) through the use of micro-inductor which is calculated and designed in standard CMOS process in this paper. The ENOB is improved 0.7 bit from 17.64 bit to 18.34 bit without any circuit just by optimized inductor value resulting in verified simulation result. Because of this feature, micro-inductor methode suggested in this paper is able to adapt a mamography that is needed high resolution so that it help to decrease patients dose amount.

Design of an Energy Management System for On-Chip Solar Energy Harvesting (온칩 태양 에너지 하베스팅을 위한 에너지 관리 시스템 설계)

  • Jeon, Ji-Ho;Lee, Duck-Hwan;Park, Joon-Ho;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.2
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    • pp.15-21
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    • 2011
  • In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

Automatic On-Chip Glitch-Free Backup Clock Changing Method for MCU Clock Failure Protection in Unsafe I/O Pin Noisy Environment (안전하지 않은 I/O핀 노이즈 환경에서 MCU 클럭 보호를 위한 자동 온칩 글리치 프리 백업 클럭 변환 기법)

  • An, Joonghyun;Youn, Jiae;Cho, Jeonghun;Park, Daejin
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.12
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    • pp.99-108
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    • 2015
  • The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

Design of the Noise Margin Improved High Voltage Gate Driver IC for 300W Resonant Half-Bridge Converter (잡음 내성이 향상된 300W 공진형 하프-브리지 컨버터용 고전압 구동 IC 설계)

  • Song, Ki-Nam;Park, Hyun-Il;Lee, Yong-An;Kim, Hyoung-Woo;Kim, Ki-Hyun;Seo, Kil-Soo;Han, Seok-Bung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.7-14
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    • 2008
  • In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

Effect of Dietary Feeding Regimens on Urea and Protein Concentration of Milk in Murrah Buffaloes

  • Roy, B.;Mehla, R.K.;Sirohi, S.K.
    • Asian-Australasian Journal of Animal Sciences
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    • v.18 no.7
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    • pp.973-979
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    • 2005
  • The present study was planned to examine the effect of different feeding regimens on milk urea concentration and milk protein concentration. The objectives are to describe the diurnal variations of milk urea (MU) concentration and to predict plasma urea (PU) concentration from MU concentration. Six lactating Murrah buffaloes were distributed in two groups and were fed two different diets in a crossover design. The diets consisted of leguminous crops as diet 1 (berseem (Trifolium alexandrinum)+concentrate mixture 1+wheat straw)) and non-leguminous crops as diet 2 (oats (Avana sativa)+concentrate mixture 2+wheat straw). All the diets were isocaloric and isonitrogenous. Each diet was fed to the animals for a period of 28 days, followed by a 10 day gap to obviate the carry over effect of the previous diet and then a switch over to the other diet. Digestibility trials were conducted on the last 7 days of each feeding period. Milk samples were collected on day 3, 7, 10, 14, 17, 21, 24 and 28 of the feeding period and blood samples were collected on the same day at morning within 30 minutes after morning milking. The average milk urea (MU) values (mg/dl) differed significantly (p<0.01) and were 44.83${\pm}$0.62 and 42.53${\pm}$0.73, respectively, for diets 1 and 2. Milk urea concentrations (mg/dl) also varied (p 0.01) among the days of feeding period, but were stabilized after 10th day of feeding period. In contrast, diets and days of feeding period had no significant effect on percent milk protein. Plasma urea concentration showed a significant (p<0.01) positive correlation (r = 0.93) with MU concentration. To predict the PU from MU the following equation was developed 'PU = 10.67${\pm}$0.76${\times}$MU (mg/dl) with $R^2$ = 0.87'. A clear diurnal variation of MU was found with lowered morning value (42.04${\pm}$0.68 mg/dl) than the evening value (45.32${\pm}$0.66 mg/dl). Present findings suggested that MU or PU concentration could be used as an indicator to monitor the feeding strategy. Plasma urea can be predicted from MU, whenever interpretation of milk urea data required consideration of diurnal variation.

A Study of the Apply Proximity Sensor for Improved Reliability Axle Detection (열차 차축검지 신뢰성 향상을 위한 근접센서 방식 Axle Counter 적용 연구)

  • Park, Jae-Young;Choi, Jin-Woo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.8
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    • pp.5534-5540
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    • 2015
  • This In the railway signaling system, applications of axle counter in addition to track circuit goes on increasing for detecting train position. Consequently, this paper compares sensor methods of axle counter with between geo-magnetism method and proximity sensor method. And it presents differences and results, to improve reliabilities of train detection and axle counting. Also, this article presents an applied result which is based on field experience, with regard to installation, considering attachment condition of sensor part for accurate axle counting. This study acquires expandability that is able to perform not only axle counting function but also various other functions (direction detection of train, speed detection of train, and so on). It was a result of a change of design in order to judge phase difference of sensors, to improve reliability of axle counting. Furthermore, it does not subordinate to characteristics (type, weight of train). And it is confirmed that the omission of axle counting was not occurred in 350km/h. This was the result of Lab test after the construction of transfer equipment of trial axle and Test Bed for axle counting. Both of them are self-productions. Through this, it prepares foundation which is able to apply not only to train detection but also to speed of passing trains, formation number of trains, detector locking condition - when the train passes the section of switch point, and level crossing devices. Furthermore, it would be judged to contribute safety train operation if proximity sensor method applies to the whole railway signaling system from now on.

Digital Data Communication System for Mobile Network System Using CC1020 Chip (CC1020 Chip을 사용한 모바일 네트워크를 위한 디지털 데이터 통신 시스템)

  • Lim, Hyun-Jin;So, Heung-Kuk
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.1
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    • pp.58-62
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    • 2007
  • Digital communication is important for reliability and mobilization of the multi-channel communication systems. Transmitting and receiving data for the mobilization should be possible in anywhere and in anytime. And this system must be designed light weight small size and low power. One are essential technology for implementing the mobile wireless communication system on the age of ubiquotos. Requirements in constructing such communication field are followings. At first data transmitting and receiving should be carried out by a simple command. Second, the device should be designed as hand-hold type and low power consumption. Third, data communication should be reliable. As one of examples, car to car system which is popular in the market is introduced here, All traffic information in highway is transmitted from one car to another by using this system which can prevent possible traffic accident. This paper shows the design of a digital data communication system with CC1020 chip. This CC1020 makes easy frequency selection and easy switch from the transmit mode to the receive mode by simple setting of a memory register in the chip. The transmit power of this system is designed 10dBm and its communication range is about 100m. The power supplied this system is 3V considered as low power. The sleep mode can be easily entered during transmit mode or receive mode. We shows the program algorithm of CC1020 and interface circuit between MCU and CC1020. We shows the Photo of the CC1020 Module and Atmega128 Module.. We analysed the receiver rate with this system.

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A Comparative Study on Power System Harmonics for Offshore Plants (해양플랜트 전력시스템의 고조파 비교분석에 관한 연구)

  • Kim, Deok-Ki;Lee, Won-Ju;Kim, Jong-Su
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.22 no.7
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    • pp.900-905
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    • 2016
  • The field of power system harmonics has been receiving a great deal of attention recently. This is primarily due to the fact that non-linear (or harmonic-producing) loads comprise an ever-increasing portion of what is handled at a typical industrial plant. The incidence rate of harmonic-related problems is low, but awareness of harmonic issues can still help increase offshore power plant system reliability. On the rare occasion that harmonics become a problem, this is either due to the magnitude of harmonics produced or power system resonance. This harmonic study used an electrical configuration for the offloading scenario of a Floating LNG (FLNG) unit, considering power load. This electrical network configuration is visible in the electrical network load flow study part of the project. This study has been carried out to evaluate the performance of an electric power system, focusing on the harmonic efficiency of an electrically driven motor system to ensure offshore plant safety. In addition, the design part of this study analyzed the electric power system of an FLNG unit to improve the safety of operation and maintenance.