• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1489-1496
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• 2009

Amorphous indium-gallium-zinc-oxide thin-film-transistors (TFTs) were modeled successfully. Dependence of TFT characteristics on structure, thickness, and equilibrium electron-density of the active layer was studied. For mono-active-layer TFTs, a thinner active layer had higher field-effect mobility. Threshold voltage showed the smallest absolute value for the 20 nm active-layer. Subthreshold swing showed almost no dependence on active-layer thickness. For the double-active-layer case, better switching performances were obtained for TFTs with bottom active layers with higher equilibrium electron density. TFTs with thinner active layers had higher mobility. Threshold voltage shifted in the minus direction as a function of the increase in the thickness of the layer with higher equilibrium electron-density. Subthreshold swing showed almost no dependence on active-layer structure. These data will be useful in optimizing the structure, the thickness, and the doping ratio of the active layers of oxide-semiconductor TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.29-34
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• 1993

In this paper, we used one-dimensional process simulator, SUPREM-II, and two-dimensional device simulator, MINIMOS 4.0 to extract optimal process parameter that can minimize degradation of device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derieved the relationship between process parameter and device characteristics. Here we have presented a method to extract process parameters from design trend curve(DTC) obtained by process and device simulations. We parameters to verify the validity of the DTC method. The experimental result of 0.8 $\mu\textrm{m}$ channel length devices that have been fabricated with optimal that reduces short channel effects, that is, good drain current-voltage characteristics, low body effects and threshold voltage of 1.0 V, high punchthrough and breakdown voltage of 12 V, low subthreshold swing(S.S) values of 105 mV/decade.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.168-168
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• 2006

Low-operating voltage organic field-effect transistors (OFETs) have been realized with high dielectric constant (${\kappa}$) polymer such as cyanoethylated poly vinyl alcohol (CR-V, ${\kappa}=12$). Since the $high-{\kappa}$polymers are likely to contain water and ionic impurities, large hysteresis and considerable leakage current are frequently observed in OFETs. To solve these problems, we cross-linked the CR-V by using a cross-linking agent. Cross-linked CR-V dielectrics showed high dielectric constant of 11.1 and good insulating properties, resulting in a high capacitance ($81nF/cm^{2}$ at 1MHz) at 120 nm of dielectric thickness. Pentacene FETs with cross-linked CR-V dielectrics exhibited high carrier mobility ($0.72\;cm^{2}/Vs$), small subthreshold swing (185 mV/dec) and little hysteresis at low-operating voltage (${\Leq}-3V$).

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.394-395
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• 2012

본 연구에서는 게이트 절연막 $SiO_2$가 증착된 Si 기판위에 스퍼터링 방식으로 투명산화막반도체 a-IGZO타겟을 사용하여 채널층을 형성하고, a-IZO타겟으로 소스/드레인층을 형성하여 박막트랜지스터를 제작하였다. 채널층의 두께 20 nm, 50 nm,100 nm에 따른 전기적인 특성을 평가하였으며, 두께 따라 문턱전압의 변화를 확인하였다. 제작된 a-IGZO 박막트랜지스터는 높은 전자이동도와 스위칭특성을 보여주었다.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.527-528
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• 2017

Current-voltage characteristics of source-overlapped gate tunnel field-effect transistor (SOG-TFET) with different channel doping concentration are proposed. Due to the gaussian doping in which the channel region near the source is highly doped and that far from the source is lightly doped, the ambipolar current was reduced, compared with the uniformly-doped SOG-TFET. On-current is almost similar in P-P-N and P-I-N structure but subthreshold swing (SS) of P-P-N TFET enhanced 5 times higher than those of P-I-N TFET. off-current and ambiploar current of the proposed SOG-TFET decrease 10 times and 100 times than those of the uniformly-doped SOG-TFET.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.20.2-20.2
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• 2009

최근 무전해 식각법을 이용한 실리콘 나노와이어 합성이 다양한 각도에서 이루어지고 있다. 무전해 식각법을 통한 나노와이어 합성은, 단결정 실리콘 기판에 촉매를 올려 기판을 식각할 수 있는데, 이 방법을 이용하여 넓은 면적의 수직방향으로 배열된 10 ~ 300nm 지름의 단결정 실리콘 나노와이어를 합성할 수 있다. 본 연구에서는 무전해 식각법으로 boron이 도핑된 p-type실리콘 기판을 식각하여 실리콘 나노와이어를 합성하였고, 단일 나노와이어의 field-effect transistor(FET) 소자가 가지는 전기적 특성에 대하여 분석하였다. 특히 무전해 식각법을 이용하여 나노와이어를 합성할 때, 촉매로 사용되는 Ag particle이 나노와이어에 미치는 영향에 대해서 분석해 보았다. FET 소자의 게이트 절연막은 가장 일반적으로 사용되는 SiO2 (300nm)와 고유전체로 잘 알려진HfO2(80nm)를 사용하여 전기적 특성을 비교하여 보았다. 한편, HfO2 박막은 atomiclayer deposition(ALD)장비를 이용하여 증착하였다. 합성된 실리콘 나노와이어의 경우 X-ray diffraction(XRD)로 결정성을 확인하였으며, high-resolution transmission electron microscopy(HRTEM)으로 결정성 및 나노와이어의 표면 형태를 확인하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, subthreshold voltage값을 평가하였다.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.163-168
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• 2014

Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.