• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1260-1265
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• 2012

This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.711-714
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• 2003

In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1840-1844
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• 2008

In this paper, the influence of channel doping concentration, which the most important factor is as double gate MOSFET is fabricated, on transport characteristics has been analyzed in the subthreshold region. The analytical model is used to derive transport model based on Poisson equation. The thermionic omission and tunneling current to have an influence on subthreshold current conduction are analyzed, and the relationship of doping concentration and subthreshold swings of this paper are compared with those of Medici two dimensional simulation, to verify this model. As a result, transport model presented in this paper is good agreement with two dimensional simulation model, and the transport characteristics have been considered according to the dimensional parameters of double gate MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.716-718
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• 2012

This paper have presented the change for subthreshold characteristics for double gate(DG) MOSFET based on scaling theory and the shape of Gaussian function. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution and consequently potential distributions have been analyzed closely for experimental results, and the subthreshold characteristics have been analyzed for the shape parameters of Gaussian function such as projected range and standard projected deviation. Since this potential model has been verified in the previous papers, we have used this model to analyze the subthreshold chatacteristics. The scaling theory is to sustain constant outputs for the change of device parameters. As a result to apply the scaling theory for DGMOSFET, we know the subthreshold characteristics have been greatly changed, and the change of threshold voltage is bigger relatively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.486-489
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• 2002

In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2015-2020
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• 2012

The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• Journal of information and communication convergence engineering
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• v.7 no.3
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• pp.361-365
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• 2009

This paper has been presented the transport characteristics of FinFET using the analytical potential model based on the Poisson's equation in subthreshold and threshold region. The threshold voltage is the most important factor of device design since threshold voltage decides ON/OFF of transistor. We have investigated the variations of threshold voltage and drain induced barrier lowing according to the variation of geometry such as the length, width and thickness of channel. The analytical potential model derived from the three dimensional Poisson's equation has been used since the channel electrostatics under threshold and subthreshold region is governed by the Poisson's equation. The appropriate boundary conditions for source/drain and gates has been also used to solve analytically the three dimensional Poisson's equation. Since the model is validated by comparing with the three dimensional numerical simulation, the subthreshold current is derived from this potential model. The threshold voltage is obtained from calculating the front gate bias when the drain current is $10^{-6}A$.