• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• Korean Journal of Materials Research
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• v.30 no.3
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• pp.117-122
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• 2020

The effects of fast neutron irradiation on the electrical and optical properties of Li (3 at%) doped ZnSnO (ZTO) thin films fabricated using a sol-gel process are investigated. From the results of Li-ZTO TFT characteristics according to change of neutron irradiation time, the saturation mobility is found to increase and threshold voltage values shift to a negative direction from 1,000 s neutron irradiation time. X-ray photoelectron spectroscopy analysis of the O 1s core level shows that the relative area of oxygen vacancies is almost unchanged with different irradiation times. From the results of band alignment, it is confirmed that, due to the increase of electron carrier concentration, the Fermi level (E_F) of the sample irradiated for 1,000 s is located at the position closest to the conduction band minimum. The increase in electron concentration is considered by looking at the shallow band edge state under the conduction band edge formed by fast neutron irradiation of more than 1,000 s.

• Nanomaterials
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• v.12 no.22
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• pp.4096-4107
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• 2022

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (I_OFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.13-20
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• 2024

This work presents a Cross-Coupled Differential Rectifier (CCDR) with an improved gate bias voltage topology, utilizing the rectifier's stage output-referred bias to increase the gate bias. The primary objective is to develop a 5.8 GHz rectifier operating at a much lower input power. The target input power is -10 dBm, which is insufficient to meet the threshold voltage of typical transistors (usually around 300 to 450 mV). Although the input power is inadequate to turn on the transistor fully, the transistor still generates a conduction swing as it operates in the sub-threshold region. Since the ratio of transconductance to current is very high in this region, an additional voltage bias is crucial to increase the swing and generate a higher output voltage. To achieve this, the proposed rectifier implements an output-connected bias for the main rectifying transistors, generating additional bias to enhance the conduction swing. Furthermore, the gate terminal is connected in parallel to the rectifier's lowest node, allowing the input voltage to be controlled by specific transistors on the proposed gate bias nodes. The design is simulated with an ideal antenna (with a 50 Ω antenna resistance) under various load and matching network conditions to match the rectifier's input impedance and maximize performance. The proposed technique, implemented using 28 nm technology, achieves a peak conversion efficiency (PCE) of 65.14%, with a total dynamic range of 21 dBm across various loads. The design generates an output of 0.8 V with a 10㏀ and 100pF load and can be extended within the dynamic range up to 1.5 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1353_1354
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• 2009

The OTFT devices had inverted staggered structures of Au/pentacene/ppMMA/ITO on PET substrate. The overall device performances of the flexible devices such as the operating voltage, the field effect mobility, the on/off ratio and the off current are somewhat worse than those of devices fabricated on glass substrates. Pentacene/ppMMA OTFT benchmarks (mobility, sub-threshold slope, on/off ratio) were comparable to that of solution cast PMMA, but below average when compared to other polymer gate dielectrics. However, threshold and drive voltages were among the lowest reported for a polymer gate dielectric, and surpassed only by ultra-thin SAM gate dielectrics.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.601-604
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• 2006

We have developed ZnO TFT array using conventional photolithography and wet etching processes. Transparent 20 nm of ultra thin ZnO film deposited by means of plasma enhanced atomic layer deposition at $100^{\circ}C$ was used for the active channel. The ZnO TFT has a mobility of $0.59cm^2/V.s$, a threshold voltage of 7.2V, sub-threshold swing of 0.64V/dec., and an on/off ratio of $10^8$.

• Electronic Materials Letters
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• v.14 no.6
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• pp.749-754
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• 2018

Previous studies have reported on the mechanical robustness and chemical stability of flexible amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) on plastic substrates both in flat and curved states. In this study, we investigate how the polyimide (PI) substrate affects hydrogen concentration in the a-IGZO layer, which subsequently influences the device performance and stability under bias-temperature-stress. Hydrogen increases the carrier concentration in the active layer, but it also electrically deactivates intrinsic defects depending on its concentration. The influence of hydrogen varies between the TFTs fabricated on a glass substrate to those on a PI substrate. Hydrogen concentration is 5% lower in devices on a PI substrate after annealing, which increases the hysteresis characteristics from 0.22 to 0.55 V and also the threshold voltage shift under positive bias temperature stress by 2 ${\times}$ compared to the devices on a glass substrate. Hence, the analysis and control of hydrogen flux is crucial to maintaining good device performance and stability of a-IGZO TFTs.