• 한국전기전자재료학회논문지
• /
• 제13권9호
• /
• pp.729-734
• /
• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회논문지SD
• /
• 제39권10호
• /
• pp.1-8
• /
• 2002

C-V 방법은 소형화된 MOSFET에서 effective channel length(L/sub eff/)를 추출하기 위한 방법 중 한가지이다. 이 방법은 critical gate bias point에서 channel length에 영향을 받지 않는 extrinsic overlap 영역의 길이(△L)를 구하여 L/sub eff/를 추출하게 된다.본 논문에서는 서로 다른 두 개의 C-V 방법에 대해 실험을 수행하였다. 그리고 실험으로 추출한 값과 2차원 소자 시뮬레이터의 결과를 비교하여 C-V 방법의 정화도를 분석하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.679-682
• /
• 2003

Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

• 대한전자공학회논문지SD
• /
• 제40권9호
• /
• pp.638-643
• /
• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• 공업화학
• /
• 제32권6호
• /
• pp.613-620
• /
• 2021

고분자전해질 연료전지의 유로 형상은 내부 유동의 균일성에 영향을 주는 변수이다. 유로 내에서 반응물 분포가 균일하지 않을 경우, 지속적인 운전 과정에서 촉매의 열화 및 고분자 막의 기계적 손상이 야기되며 연료전지의 내구 수명 저하로 이어진다. 연료전지에서 원활한 반응물 공급과 균일한 농도 분포를 위하여 유로 형상에 관한 연구들이 활발히 진행되고 있다. 유로의 배플은 유체의 강제 대류를 야기해 연료전지의 성능을 개선할 수 있고, 유로 중간에 새로운 반응물 공급 통로(서브 채널)를 만들어 반응물 농도 증가와 원활한 물 배출로 물질 전달 손실을 감소시킬 수 있다. 본 연구에서는 전산 유체 계산을 통하여 블록과 서브 채널을 적용한 유로가 연료전지의 전류밀도와 산소 농도에 미치는 영향을 분석하였다. 블록과 서브 채널이 유로에 구성되었을 때, 한계전류밀도가 증가하였고 블록 후단의 산소 농도가 회복되었다. 블록이 2개 이상 있을 때 블록 사이에 서브 채널을 배치할 경우 전류밀도 증가 폭이 더욱 커졌다. 또한 추가 공급되는 공기의 공급 위치에 따른 산소 농도를 분석하여 서브 채널이 블록 후단의 낮아진 산소 농도를 회복할 수 있었다.

• Bulletin of the Korean Chemical Society
• /
• 제31권7호
• /
• pp.2031-2035
• /
• 2010

A triple-probe channel type chemosensor based on an $NO_2S_2$-macrocycle functionalized with phenyltricyanovinyl group was synthesized and its sensing characteristics were examined. The pink-red solution of L changed selectively to pale yellow upon addition of $Hg^{2+}$. The selective fluorometric response of L to all the tested metal ions was studied. The results showed that a large enhancement of the fluorescence of L was observed only in the case of $Hg^{2+}$. In addition, L showed large anodic shift (~ 0.3 V) for the addition of excess $Hg^{2+}$. Through above three observed results by the different techniques, we confirmed that the proposed chemosensor acts as the multiple-probe channel sensing material. The crystal structure of mercury(II) nitrate complexs of L which shows a 1-D polymer network with a formula $[Hg_2(L)_2(NO_3)_2({\mu}-NO_3)_2]_n$ was also reported.

• 한국전기전자재료학회논문지
• /
• 제31권3호
• /
• pp.135-140
• /
• 2018

Atomically thin $MoS_2$ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, $MoS_2$ single-crystal as a transistor channel after transfer onto a $SiO_2/Si$ substrate. The $MoS_2$ FETs displayed n-channel characteristics with an electron mobility of $0.05cm^2/V-sec$, and a current on/off ratio of $I_{ON}/I_{OFF}{\simeq}5{\times}10^4$. Application of bottom-gate voltage stresses, however, increased the interface charges on $MoS_2/SiO_2$, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

• 한국전기전자재료학회논문지
• /
• 제36권2호
• /
• pp.129-135
• /
• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
• /
• pp.180-183
• /
• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• The Korean Journal of Physiology and Pharmacology
• /
• 제28권5호
• /
• pp.413-422
• /
• 2024

Group I metabotropic glutamate receptors (mGluRs) modulate postsynaptic neuronal excitability and epileptogenesis. We investigated roles of group I mGluRs on low extracellular Mg²⁺ concentration ([Mg²⁺]_o)-induced epileptiform activity and neuronal cell death in the CA1 regions of isolated rat hippocampal slices without the entorhinal cortex using extracellular recording and propidium iodide staining. Exposure to Mg²⁺-free artificial cerebrospinal fluid can induce interictal epileptiform activity in the CA1 regions of rat hippocampal slices. MPEP, a mGluR 5 antagonist, significantly inhibited the spike firing of the low [Mg²⁺]_o-induced epileptiform activity, whereas LY367385, a mGluR1 antagonist, did not. DHPG, a group 1 mGluR agonist, significantly increased the spike firing of the epileptiform activity. U73122, a PLC inhibitor, inhibited the spike firing. Thapsigargin, an ER Ca²⁺-ATPase antagonist, significantly inhibited the spike firing and amplitude of the epileptiform activity. Both the IP₃ receptor antagonist 2-APB and the ryanodine receptor antagonist dantrolene significantly inhibited the spike firing. The PKC inhibitors such as chelerythrine and GF109203X, significantly increased the spike firing. Flufenamic acid, a relatively specific TRPC 1, 4, 5 channel antagonist, significantly inhibited the spike firing, whereas SKF96365, a relatively non-specific TRPC channel antagonist, did not. MPEP significantly decreased low [Mg²⁺]_o DMEM-induced neuronal cell death in the CA1 regions, but LY367385 did not. We suggest that mGluR 5 is involved in low [Mg²⁺]_o-induced interictal epileptiform activity in the CA1 regions of rat hippocampal slices through PLC, release of Ca²⁺ from intracellular stores and PKC and TRPC channels, which could be involved in neuronal cell death.