• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.318-323
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• 2015

We present a new way to create a thermally stable, highly strained germanium (Ge) optical resonator using a novel Ge-on-dual-insulators substrate. Instead of using a conventional way to undercut the oxide layer of a Ge-on-single-insulator substrate for inducing tensile strain in germanium, we use thin aluminum oxide as a sacrificial layer. By eliminating the air gap underneath the active germanium layer, we achieve an optically insulating, thermally conductive, and highly strained Ge resonator structure that is critical for a practical germanium laser. Using Raman spectroscopy and photoluminescence experiments, we prove that the novel geometry of our Ge resonator structure provides a significant improvement in thermal stability while maintaining good optical confinement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.12
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• pp.757-761
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• 2017

The computational fourier-transform moire (CFTM) method has been briefly explained and this method was used to perform strain analysis of a misfit dislocation in a strained $Si/Si_{0.55}Ge_{0.45}$ layer. An essential advantage of the CFTM method is that it does not require unwrapping, such that errors due to improper unwrapping can be excluded. The analysis results revealed that the Si layer was grown with tensile stress on $Si_{0.55}Ge_{0.45}$ and lattice constant of the Si layer along the growth direction was 1.9% smaller than that of $Si_{0.55}Ge_{0.45}$. On the other hand, strain of the misfit dislocation in the strained $Si/Si_{0.55}Ge_{0.45}$ layer was maximum at the dislocation core due to an extra half-plane and the $e_{xx}$ and $e_{yy}$ values were positive and negative, respectively, along the direction of a burgers vector.

• ETRI Journal
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• v.28 no.2
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.12-17
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• 2011

In this work, the analog performances of n-MOSFET fabricated on strained-Si/relaxed Si buffer layer with Ge mole fractions and thermal annealing temperatures after device fabrication have been characterized in Depth. The effective electron mobility was increased with the increase of Ge mole fraction for all annealing temperatures. However the effective electron mobility was decreased at the Ge mole fraction of 32%. The analog performances were enhanced with the increase of Ge mole fraction at the room temperature but they were degraded at the Ge mole fraction of 32%. Since the degradation of the effective electron mobility of strained-Si layer is more significant than one of conventional Si layer at elevated temperature, the degradation of analog performances of SGOI devices were increased than those of SOI devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.2
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• pp.66-70
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• 2006

Various kind of structural defects are observed to be present on the oxidized surface of the silicon crystal which was previously damaged mechanically. The formation of such defects was found to depend on the amount of damage induced and the temperature of thermal oxidation. It was confirmed by the measurement of minority carrier life time that gettering capability decreases as the size of the defects increase. The strained layer which is formed due to smaller amount of damage or lower oxidation temperature believed to has higher capability of gettering over defects like dislocation loops or stacking faults.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.185-197
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• 1996

We have adopted the strain compensated PBH(planar buried heterostructure) - LD in which the MQW active layer consisted of 1.4% compressively strained GainAsP (E$_{g}$ = 0.905eV) wells and 0.7% tensile strained GaInAsP(E$_{g}$ = 1.107eV) barriers grown by metal organic vapor phase epitaxy (MOVPE). We hav einvestigated effects of number of wells and the structure of the separate confinement heterostructure (SCH) layer in the strain-compensated MQW-PBH-LD. The threshold current, the external quantum efficiency, the transparency current density J$_{o}$, and the gain constant .beta. have been evaluated for uncoated MQW-PBH-LD. As the number of wells increases, the internal quantum efficiency and the transparency current density decreases, whereas the gain contant increases. The small width of the SCH layer shows the large internal quantum efficiency. The small internal loss and the large gain constant have been obtained by inserting the large bandgap SCH layer.