• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.618-620
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• 1997

A $50{\times}50{\mu}m^2$ aluminum micromirror array is fabricated using shadow evaporation process. The fabrication process is very simple with use of shadow evaporation process, and the micromirror array has a high fill-factor. The static and dynamic characteristics such as deflection angle vs. applied voltage, step response, and frequency response are measured using a contact free optical measurement technique. The downward threshold voltage was 8 V, step response time was $13.5{\mu}s$ when 32 V step voltage applied, and a resonance observed at 11kHz. The lifetime of micromirror with anti-stiction coating was tested and micromirror operated successfully over 200 million cycles of touch-down operations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• 한국전기전자재료학회논문지
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• 제30권9호
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• pp.566-571
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• 2017

A soft baking process was used to enhance the electrical characteristics of solution-processed indium-zincoxide (IZO) thin-film transistors (TFTs). We demonstrate a stable soft baking process using a hot plate in air to maintain the electrical stability and improve the electrical performance of IZO TFTs. These oxide transistors exhibited good electrical performance; a field-effect mobility of $7.9cm^2/Vs$, threshold voltage of 1.4 V, sub-threshold slope of 0.5 V/dec, and a current on/off ratio of $2.9{\times}10^7$ were measured. To investigate the static response of our solutionprocessed IZO TFTs, simple resistor load type inverters were fabricated by connecting a resistor (5 or $10M{\Omega}$). Our IZO TFTs, which were manufactured using the soft baking process at a baking temperature of $120^{\circ}C$, performed well at the operating voltage, and are therefore a good candidate for use in advanced logic circuits and transparent display backplanes.

• 한국전기전자재료학회논문지
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• 제30권6호
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• pp.345-348
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• 2017

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from $1{\times}10^{15}cm^{-3}$ to $5{\times}10^{16}cm^{-3}$ and the thickness from $0{\mu}m$ to $9{\mu}m$. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

• 한국전기전자재료학회논문지
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• 제31권1호
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• pp.50-54
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• 2018

In this study, a femtosecond laser pre-annealing technology based on indium zinc oxide (IZO) thin-film transistors (TFTs) was investigated. We demonstrated a stable pre-annealing process to analyze the change in the surface structures of thin-films, and we improved the electrical performance. Furthermore, static and dynamic electrical characteristics of IZO TFTs with n-channel inverters were observed. To investigate the static and dynamic responses of our solution-processed IZO TFTs, simple resistor-load-type inverters were fabricated by connecting a $1-M{\Omega}$ resistor. The femtosecond laser pre-annealing process based on IZO TFTs showed good performance: a field-effect mobility of $3.75cm_2/Vs$, an $I_{on}/I_{off}$ ratio of $1.8{\times}10^5$, a threshold voltage of 1.13 V, and a subthreshold swing of 1.21 V/dec. Our IZO-TFT-based N-MOS inverter performed well at operating voltage, and therefore, is a good candidate for advanced logic circuits and display backplane.

• 대한전자공학회논문지SD
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• 제41권7호
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• pp.37-41
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• 2004

We have formulated an empirical analytic model for the static characteristics of implanted vertical-cavity surface-emitting lasers (VCSELs). Specifically, we have derived analytic formulas for the threshold current, slope efficiency, dynamic resistance, and the output power and forward voltage at the operation current of 12 ㎃ in terms of the implant and metal-aperture radii by fitting the measured results. The radii of the metal aperture and implant mask of the 850 nm VCSELs range from 4 to 12.5 ${\mu}{\textrm}{m}$ and 7 to 17.5 ${\mu}{\textrm}{m}$ respectively. The model shows the way of tailoring the VCSEL characteristics by changing the mask dimensions only.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 전기학회논문지
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• 제65권5호
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• pp.785-793
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• 2016

This paper analyzes an LCL-type isolated dc-dc converter operating for constant output voltage in the continuous conduction mode(CCM) with resistances of parasitic losses-static drain-source on resistance of power switch, ESR of resonant network(L-C-L)-using a high loaded quality factor Q assumptions and fourier series techniques. Simple analytical expressions for performance characteristics are derived under steady-state conditions for designing and understanding the behavior of the proposed converter. The voltage-driven rectifier is analyzed, taking into account the diode threshold voltage and the diode forward resistance. Experimental results measured for a proposed converter at low input voltage and various load resistances show agreement to the theoretical performance predicted by the analysis within maximum 4% error. Especially in the case of low output voltages and large loads, It is been observed that introduction of both rectifier and the parasitic components of converter had considerable effect on the performance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.63-63
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• 2009

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

• 한국산업정보학회논문지
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• 제17권4호
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• pp.17-23
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• 2012

초저전력 설계나 에너지 수확 활용은 동적 전력과 정적 전력 사이의 균형을 이루는 점에 근접하는 문턱전압이하의 매우 낮은 전압에서 작동하는 디지털 시스템을 요구한다. 이런 동작 모드에서 일반적인 논리회로의 지연 변화는 매우 크게 된다. 따라서, 본 논문에서 MOSFET 나노 공정기술에서 전력소비를 줄이면서 여러 가지 공정 변이의 영향을 받지 않는 비동기 방식의 NCL (Null conventional logic)을 사용한 저전력 논리회로 설계 방법을 제안하고자 한다. 제안된 NCL 회로는 45nm의 공정기술에서 0.4V의 공급전압을 사용하였고, 각 NCL회로는 속도와 전력에 의해서 일반적인 동기식 회로와 비교되었다.