References
- Kyung Ki Kim, "Minimal Leakage Pattern Generator," 한국산업정보학회논문지, V. 16, No. 5, pp.1-8, 2011년 12월.
- Kyung Ki Kim, "The Impact of TDDB Failure on Nanoscale CMOS Digital Circuits," 한국산업정보학회논문지, V. 17, No. 3, pp.27-34, 2012년 6월. https://doi.org/10.9723/jksiis.2012.17.3.027
- I. Sutherland and S. Fairbanks, "Gasp; a Minimal FIFO Control," Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems, 2001, pp.46-53.
- M. Singh and S. M. Nowick, "MOUSET- RAP: High-speed Transition- signaling Asynchronous Pipelines," IEEE Trans. on VLSI Systems, Vol.15, No.6, June 2007, pp.684-698. https://doi.org/10.1109/TVLSI.2007.898732
- S. Schuster and P. Cook, "Low-power Synchronous-to-asynchronous-to-synchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5 GHz," IEEE J. of Solid-State Circuits, Vol.38, No.4, Apr. 2003, pp.622-630. https://doi.org/10.1109/JSSC.2003.809512
- Scott Hauck, "Asynchronous Design Methodologies: An Overview", Proceeding of the IEEE, Vol. 86, No. 1, Jan. 1995, pp. 69-93.
- B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, "Implementation of Design For Test for Asynchronous NCL Designs", The 2005 International Conference on Computer Design, pp. 78-84, June 2005.
- J. Pangjun and S.S. Sapatnekar, "Low- power Clock Distribution Using Multiple Voltages and Reduced Swings," IEEE Trans. on VLSI Systems, Vol.10, No.2, June 2002, pp.309-318. https://doi.org/10.1109/TVLSI.2002.1043334
- J. Kessels and R. Marston, "Designing Asynchronous Standby Circuits for a Low- Power Pager," Proc. of the IEEE, Vol.87, No.2, Feb. 1999, pp.257-267. https://doi.org/10.1109/5.740019
- L.S. Nielsen and J. Sparso, "Designing Asynchronous Circuits for Low Power: an IFIR Filter Bank for a Digital Hearing Aid," Proc. of the IEEE, Vol.87, No.2, Feb. 1999, pp.268-281. https://doi.org/10.1109/5.740020
- H.Van Gageldonk et al., "An Asynchronous Low-power 80c51 Microcon- troller," Proc. International Symposium Advanced Research in Asynchronous Circuits and Systems, 1998, pp. 96-107.
- Roig, Formal Verification and Testing of Asynchronous Circuits, Ph.D. Dissertation, Universitat Politecnica de Catalunya, May 1997.
- J. Sparsø and S. Furber, "Principles of Asynchronous Circuit Design: a System Perspective," Kluwer Academic Publishers, 2001.
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