• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.8-16
• /
• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• Proceedings of the Korean Society for Food Science of Animal Resources Conference
• /
• 2000.11a
• /
• pp.1-14
• /
• 2000

The Near Infrared region of the energy spectrum was first discovered by Hershel in the year 1800. The principles of NIR is based on light absorption of specific organic chemical bonds. The absorption at each wavelength is measured and a spectre is obtained. The spectre is then treated mathematically and with the absorption data is converted to absolute units via a calibration. In the last two decades it has developed dramatically. With the invention of computers and the ability to treat a large amount of data in a very short time the use of NIR for many different purposes has developed very fast. During the last decade with the aid of very powerful PC's the application of NIR technology has become even more widespread. Now or days development of very robust calibrations can be done in a relatively short time with a minimum of resources. The use of Near Infrared Spectroscopy (NIR) in the Meat industry is relatively new. The first installations were taken into operation in the 80ties. The Meat Industry in often referred to as rather conservative and slow to embrace new technologies, they stay with the old and proven methods. The first NIR instruments used by the Meat Industry, and most other industries, were multipurpose build, which means that the sample presentation was not well suited to this particular application, or many other applications for that sake. As the Meat Industry grows and develops to meet the demands of the modern markets, they realise the need for better control of processes and final products. From the early 90 ties and onward the demand for 'rear time' rapid results starts growing, and some suppliers of NIR instruments (and instruments based on other technologies, like X-ray) start to develop and manufacture instrumentation dedicated to the particular needs of the Meat Industry. Today it is estimated that there are approximately 2000 rapid instruments placed in the Meat industry world-wide. By far most of these are used as at-line or laboratory installations, but the trend and need is moving towards real on-line or in-line solutions. NIR is the most cost effective and reproducible analytical procedure available for the twenty first century.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.60-67
• /
• 2010

We designed Average Current Control PFC IC which has make the average value of boost inductor current became the shape of sine wave. Designed IC has fixed frequency of 75kHz to meet EMI standard requirement. And also RC compensation loop has been designed into the error amp and the current amp, in order that it has wide bandwidth for high speed control. And we use the oscillator which generates by square wave and triangle wave, and add to UVLO, OVP, OCP, TSD which is in order to operate stability. We simulated by using Spectre of Cadence to verify the unity power factor function and various protection circuits and fabricated in a $1{\mu}m$ High Voltage(20V) CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.73-78
• /
• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of Korea Multimedia Society
• /
• v.14 no.5
• /
• pp.614-621
• /
• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.2
• /
• pp.291-298
• /
• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.5
• /
• pp.769-776
• /
• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.5
• /
• pp.777-784
• /
• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.122-122
• /
• 2009

최근 PC의 성능이 향상되면서, 고성능의 전원공급 장치가 요구되고 있다. 특히 CPU에 대전력을 공급하는 싱크로너스 벅 컨버터는 파워 MOSFET을 구동하기 위해 별도의 구동 IC가 필요하다. 본 논문은 adaptive 지연을 이용하여 파워 MOSFET을 구동하는 싱크로너스 벅 구동 IC를 설계하였다. 고정밀도의 밴드캡 기준회로와 비교기를 이용하여 30 ns의 adaptive 지연을 생성하며, 전력소모를 줄이기 위해 저전압에서 동작하는 UVLO(under voltage lock out)를 설계하였다. 또한 상단 파워 MOSFET을 구동하기 위하여 부트스트랩 방식을 이용하며, 부트스트랩 다이오드를 IC 내부에 내장하여 컨버터의 설계비용을 줄였다. 설계한 구동 IC의 동작 전압 범위는 8 V - 15 V이며, 출력 전류는 최대 2A이다. 싱크로너스 벅 구동 IC는 $0.5\;{\mu}m$ BiCMOS(Bipolar-CMOS) 공정 파라미터를 사용하여 설계되었으며, 시뮬레이션은 Cadence사의 Spectre를 이용하였다.

• Proceedings of the KIEE Conference
• /
• 2008.10a
• /
• pp.161-162
• /
• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed RFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블록은 Cadence spectre를 이용하여 검증하였다.