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http://dx.doi.org/10.9717/kmms.2011.14.5.614

Design of a Wide Tuning Range DCO for Mobile-DTV Applications  

Song, Sung-Gun (전남대학교 전자컴퓨터공학과)
Park, Sung-Mo (전남대학교 전자컴퓨터공학과)
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Abstract
This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.
Keywords
Mobile-DTV; ADPLL; DCO; Oscillator; Delay Cell;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, "A Clock Generator with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications," IEEE J. Solid-State Circuits, Vol.41, No.6, pp.1275- 1285, 2006.   DOI   ScienceOn
2 Chen Juan, Fang Shou-hai, and Chen Xin, "A Novel DCPLL with Small-Area and Low- Power DCO for SoC Applications," IEEE Solid-State and Integrated-Circuit Technology Conf, pp.1867-1870, 2008.
3 T. Olsson and P. Nilsson, "A Digitally Controlled PLL for SoC Application," IEEE J. Solid-State Circuits, Vol.39, No.5, pp.751- 760, 2004.   DOI
4 Staszewski. R. B, Dirk Leipold, Khurram Muhammad, and Poras T. Balsara, "Digitally Controlled Oscillator(DCO)-Based Architecture for RF Frequency Synthesis in a Deep- Submicrometer CMOS Process," IEEE Transactions on Circuits and Systems II-analog and digital signal processing, Vol.50, No.11, pp.815-823, 2003.   DOI   ScienceOn
5 J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI," IEEE J. Solid- State Circuits, Vol.43, No.1, pp.42-51, 2008.   DOI
6 R.-J. Yang and S.-I. Liu, "A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $\mu$m CMOS Technology," IEEE J. Solid-State Circuits, Vol.42, No.1, pp.2338-2347, 2007.   DOI
7 Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, and Hong-June Park, "An Interpolating Digitally Controlled Oscillator for a Wide- Range All-Digital PLL," IEEE transactions on circuits and system, Vol.56, No.9, pp.2055-2063, 2009.   DOI
8 Tomar A., Pokharel R.K., Nizhnik O., and Kanaya H., Yoshida K., "Design of 1.1 ㎓ Highly Linear Digitally-Conrolled Ring Oscillator with Wide Tuning Range," RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, pp. 82-85, 2007.
9 G. Jovanovic, M. Stojcev, "Voltage Controlled Delay Line for Digital Signal," Facta Universitatis, Series: Electronics and Energetic, Vol. 16. No.2, pp.215-232, 2003.   DOI
10 Liangge Xu, Kari Stadius, Tapio Rapinoja, and Jussi Ryynanen, "Agile Frequency Synthesizer for Cognitive Radios," IEEE Circuit Theory and Design Conf, pp.275-278, 2009.
11 Sang-Myeong Shin, Dong-Gi Im, and Min-Soo Jung, "Efficient Native Processing Modules for Interactive DTV Middleware Based on the Small Footprint Set-Top Box," Journal of Korea Multimedia Society, Vol.9, No.12, pp.1617-1627, 2006.
12 Bon-Kee Kim, Tae-Wook Kim, Young-Ho Cho, Min-Su Jeong, Se-Yeob Kim, Hee- Young Yoo, Seong-Mo Moon, Tae-Ju Lee, Jin-Kyu Lim, and Bo-Eun Kim, "A 100㎽ Dual-Band CMOS Mobile-TV Tuner IC for -T-DMB/ DAB and ISDB-T," IEEE Solid- State Circuits Conf, pp.2534-2543. 2006.
13 Jen-Shiun Chiang and Kuang-Yuan Chen, "The Design of an All-Digital Phase-Locked Loop with Small DCO Hardware and Fast Phase Lock," IEEE Transactions on Circuits and Systems II-analog and digital signal processing, Vol.46, No.7, pp.945-950, 1999.   DOI   ScienceOn