• 제목/요약/키워드: Solder Interconnection

검색결과 61건 처리시간 0.03초

Fine-Pitch Solder on Pad Process for Microbump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Choi, Kwang-Seong;Eom, Yong-Sung
    • ETRI Journal
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    • 제35권6호
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    • pp.1152-1155
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    • 2013
  • A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

Electrical Interconnection with a Smart ACA Composed of Fluxing Polymer and Solder Powder

  • Eom, Yong-Sung;Jang, Keon-Soo;Moon, Jong-Tae;Nam, Jae-Do
    • ETRI Journal
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    • 제32권3호
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    • pp.414-421
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    • 2010
  • The interconnection mechanisms of a smart anisotropic conductive adhesive (ACA) during processing have been characterized. For an understanding of chemorheological mechanisms between the fluxing polymer and solder powder, a thermal analysis as well as solder wetting and coalescence experiments were conducted. The compatibility between the viscosity of the fluxing polymer and melting temperature of solder was characterized to optimize the processing cycle. A fluxing agent was also used to remove the oxide layer performed on the surface of the solder. Based on these chemorheological phenomena of the fluxing polymer and solder, an optimum polymer system and its processing cycle were designed for high performance and reliability in an electrical interconnection system. In the present research, a bonding mechanism of the smart ACA with a polymer spacer ball to control the gap between both substrates is newly proposed and investigated. The solder powder was used as a conductive material instead of polymer-based spherical conductive particles in a conventional anisotropic conductive film.

Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Eom, Yong-Sung;Choi, Kwang-Seong
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.55-59
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    • 2015
  • Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

Interconnection Technology Based on InSn Solder for Flexible Display Applications

  • Choi, Kwang-Seong;Lee, Haksun;Bae, Hyun-Cheol;Eom, Yong-Sung;Lee, Jin Ho
    • ETRI Journal
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    • 제37권2호
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    • pp.387-394
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    • 2015
  • A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

150℃이하 저온에서의 미세 접합 기술 (Low Temperature bonding Technology for Electronic Packaging)

  • 김선철;김영호
    • 마이크로전자및패키징학회지
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    • 제19권1호
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    • pp.17-24
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    • 2012
  • Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

Highly Reliable Solder ACFs FOB (Flex-on-Board) Interconnection Using Ultrasonic Bonding

  • Kim, Yoo-Sun;Zhang, Shuye;Paik, Kyung-Wook
    • 마이크로전자및패키징학회지
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    • 제22권1호
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    • pp.35-41
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    • 2015
  • In this study, in order to improve the reliability of ACF interconnections, solder ACF joints were investigated interms of solder joint morphology and solder wetting areas, and evaluated the electrical properties of Flex-on-Board (FOB) interconncections. Solder ACF joints with the ultrasonic bonding method showed excellent solder wetting by broken solder oxide layers on solder surfaces compared with solder joints with remaining solder oxide layer bonded by the conventional thermo-compression (TC) bonding method. When higher target temperature was used, Sn58Bi solder joints showed concave shape due to lower degree of cure of resin at solder MP by higher heating rate. ACFs with epoxy resins and SAC305 solders showed lower degree of resin cure at solder MP due to the slow curing rate resulting in concave shaped solder joints. In terms of solder wetting area, solder ACFs with $25-32{\mu}m$ diameters and 30-40 wt% showed highest wetted solder areas. Solder ACF joints with the concave shape and the highest wetting area showed lower contact resistances and higher reliability in PCT results than conventional ACF joints. These results indicate that solder morphologies and wetting areas of solder ACF joints can be controlled by adjustment of bonding conditions and material properties of solder and polymer resin to improve reliability of ACF joints.

INTERCONNECTION TECHNOLOGY IN ELECTRONIC PACKAGING AND ASSEMBLY

  • Wang, Chunqing;Li, Mingyu;Tian, Yanhong
    • 대한용접접합학회:학술대회논문집
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    • 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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    • pp.439-449
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    • 2002
  • This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

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Si웨이퍼의 이방성 식각 특성 및 Si carrier를 이용한 플립칩 솔더 범프제작에 관한 연구 (The characterization of anisotropic Si wafer etching and fabrication of flip chip solder bump using transferred Si carrier)

  • 문원철;김대곤;서창재;신영의;정승부
    • 대한용접접합학회:학술대회논문집
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    • 대한용접접합학회 2006년도 춘계 학술대회 개요집
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    • pp.16-17
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    • 2006
  • We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

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쏠더를 이용한 웨이퍼 레벨 실장 기술 (A novel wafer-level-packaging scheme using solder)

  • 이은성;김운배;송인상;문창렬;김현철;전국진
    • 반도체디스플레이기술학회지
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    • 제3권3호
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    • pp.5-9
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    • 2004
  • A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

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