• 대한전자공학회논문지SD
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• 제38권2호
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• pp.87-94
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• 2001

DRAM에서 셀 캐패시터의 누설 전류 영향을 고려하여 소프트 에러율을 예측하였다. DRAM의 동작 과정에서 누설 전류의 영향으로 셀 캐패시터는 전하량이 감소하고, 이에 따른 소프트 에러율을 DRAM의 각 동작 모드에 대하여 계산하였다. 누설 전류가 작을 경우에는 /bit mode가 소프트 에러에 취약했지만, 누설전류가 커질수록 memory 모드가 소프트 에러에 가장 취약함을 보였다. 실제 256M급 DRAM의 구조에 적용하여, 셀 캐패시턴스, bit line 캐패시턴스, sense amplifier의 입력 전압 감도들이 변화할 때 소프트 에러에 미치는 영향을 예측하였고, 이 결과들은 차세대 DARM 연구의 최적 셀 설계에 이용될 수 있다.

• 전자공학회논문지D
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• 제36D2호
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• pp.55-61
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• 1999

DRAM에서 알파 입자의 입사에 의한 소프트 에러율을 예측하는 시뮬레이터를 개발하였다. 새로운 시뮬레이터는 수집 전하량에 대한 해석적 모델을 사용함으로서 소자 시뮬레이터나 몬테칼로 시뮬레이터를 사용하는 기존의 예측 시뮬레이터에 비하여 계산시간을 크게 감소하였다. DRAM에서 발생하는 소프트 웨어의 모드를 분석한 결과, bit-bar 모드에 의한 소프트 에러율이 가장 큰 것을 알 수 있었으며 256M DRAM의 셀 구조에 대한 소프트 에러율을 시뮬레이션하여 storage 캐패시턴스가 약 5fF의 margin을 갖고있음을 밝혔다.

• 한국경영과학회지
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• 제31권3호
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• pp.1-10
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• 2006

In this paper we deal with a cell planning issue arisen in a CDMA based multicast network. In a CDMA based wireless network, a terminal can significantly reduce the bit error rate via the cohesion of data streams from multiple base stations. In this case, multiple base stations have to be operated according to a common time line. The cells whose base stations are operated as such are called soft-combined cells. Therefore, a terminal can take advantage of error rate reduction, if the terminal is in a soft-combined cell and at least one neighboring cell is also soft-combined. However, as soft-combining operation gives heavy burden to the network controller, the limited number of cells can be soft-combined. Our problem us to find a limited number of soft-combined cells such that the benefit of the soft-combining operation is maximized.

• 한국전기전자재료학회논문지
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• 제19권6호
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• pp.507-511
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• 2006

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

• 전기학회논문지
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• 제57권1호
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• KIEE International Transactions on Electrophysics and Applications
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• 제5C권6호
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• pp.242-245
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• 2005

We compared and analyzed ASER (Accelerated Soft Error Rate) for cell structures and metal plate capacitance in the fabricated 16M SRAM. Application of the BNW (Buried NWELL) lowered the ASER value compared to the normal well structure. By applying the metal plate capacitor with the BNW, the lowest ASER value can be obtained. The thinner oxide thickness of the metal plate capacitor provides higher capacitance and lower ASER value. The ASER is improved from 2200 FIT to 1000 FIT after sole application of the BNW. However, it is dramatically improved to 15 FIT once the metal plate capacitor is additionally applied.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권1호
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• pp.15-18
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• 2003

The characteristics of accelerated soft error rate (ASER) for fabricated 8M SRAM are evaluated for various well structures. The application of the Buried NWell (BNW) and the variations of each well structure, well dose in process conditions are checked by ASER failure in time (FIT) in terms of reliability. The application of only the BNW shows the lowest ASER FIT value. The BNW added to the Buried PWell (BPW) shows a 200% increase and the BNW plus the Striped BPW (SBPW) shows a 100% increase compared to applying the BNW. The cases of applying SBPW show very high ASER FIT.

• Journal of Information Processing Systems
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• 제7권3호
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• pp.435-446
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• 2011

Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique significantly increases the verification workload on the processor resources, resulting in severe performance degradation. This paper presents a pro-active verification management approach to mitigate the verification workload to increase its performance with a minimal effect on overall reliability. An anomaly-speculation-based filter checker is proposed to guide a verification priority before the re-execution process starts. This technique is accomplished by exploiting a value similarity property, which is defined by a frequent occurrence of partially identical values. Based on the biased distribution of similarity distance measure, this paper investigates further application to exploit similar values for soft error tolerance with anomaly speculation. Extensive measurements prove that the majority of instructions produce values, which are different from the previous result value, only in a few bits. Experimental results show that the proposed scheme accelerates the processor to be 180% faster than traditional fully-fault-tolerant processor with a minimal impact on overall soft error rate.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2020년도 추계학술대회
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.

• Nuclear Engineering and Technology
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• 제40권1호
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• pp.69-76
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• 2008

Most pressurized water reactors use Venturi flow meters to measure the feedwater flow rate. However, fouling phenomena, which allow corrosion products to accumulate and increase the differential pressure across the Venturi flow meter, can result in an overestimation of the flow rate. In this study, a soft-sensing model based on fuzzy support vector regression was developed to enable accurate on-line prediction of the feedwater flow rate. The available data was divided into two groups by fuzzy c means clustering in order to reduce the training time. The data for training the soft-sensing model was selected from each data group with the aid of a subtractive clustering scheme because informative data increases the learning effect. The proposed soft-sensing model was confirmed with the real plant data of Yonggwang Nuclear Power Plant Unit 3. The root mean square error and relative maximum error of the model were quite small. Hence, this model can be used to validate and monitor existing hardware feedwater flow meters.