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http://dx.doi.org/10.4313/JKEM.2006.19.6.507

Reliability on Accelerated Soft Error Rate in Static RAM of Thin Film Transistor Type  

Kim Do-Woo (한국폴리텍여자대학 디지털디자인과)
Wang Jin-Suk (충남대학교 전자공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.19, no.6, 2006 , pp. 507-511 More about this Journal
Abstract
We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer
Keywords
Thin film transistor; SRAM; Soft error rate; FIT; Well; Polysilicon;
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