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Accelerated Soft Error Rate Study with Well Structures  

Kim, Do-Woo (Memory R & D, Hynix Semiconductor Inc.,)
Gong, Myeong-Kook (Memory R & D, Hynix Semiconductor Inc.)
Wang, Jin-Suk (Dept. of Electrical and Electronic Engineering, Chungnam National University)
Publication Information
KIEE International Transactions on Electrophysics and Applications / v.3C, no.1, 2003 , pp. 15-18 More about this Journal
Abstract
The characteristics of accelerated soft error rate (ASER) for fabricated 8M SRAM are evaluated for various well structures. The application of the Buried NWell (BNW) and the variations of each well structure, well dose in process conditions are checked by ASER failure in time (FIT) in terms of reliability. The application of only the BNW shows the lowest ASER FIT value. The BNW added to the Buried PWell (BPW) shows a 200% increase and the BNW plus the Striped BPW (SBPW) shows a 100% increase compared to applying the BNW. The cases of applying SBPW show very high ASER FIT.
Keywords
Soft error rate; FIT; Well; Buried NWell; Buried Pwell;
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Times Cited By KSCI : 1  (Citation Analysis)
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