• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.47-55
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• 2015

To verify the function of vehicle is becoming more and more difficult because many electronic control units have been embedded in vehicle with development of electronics industry. The reliability of vehicle should be considered above all important because malfunction of vehicle can cause damage of human life. In this paper, defect diagnosis platform based on CAN network is proposed to improve the reliability of vehicle. Reliability of vehicle is significantly increased by adopting the structural test via dedicated test path after manufacturing. Besides, the test cost is reduced because additional test pins are not required.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.3
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• pp.156-162
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• 2003

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.140-150
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• 2006

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.39-47
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• 2016

In this paper, we propose vehicle SoC fault diagnosis platform using FlexRay protocol in order to detect the faults of semiconductor control chip even after vehicle production. Before FlexRay protocol by sending NFI (Null Frame Indicator) bit among the header segment and a specific identifier in the payload segment of FlexRay frame, this technique can be distinguishable from normal mode and test mode. By using this technique, it is possible to detect the faults such as performance degradation of vehicle network system caused by the aging or several problems of vehicle semiconductor chip. Also high reliability and safety of vehicle can be maintained by using structural test for vehicle SoC fault detection.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.994-1000
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• 2004

It is growing the application of the removal ground anchor with tension force for earth retaining constructions in the downtown. Nowadays, we can find the compression dispersion anchor on many site. But, it is occur some probelems in behabior of anchors because of impossible to tense p.c strand uniformly with existing equipment due to different length of p.c strand. So we tried to tense each p.c strand uniformly with auto back equipment in-situ test. This study compared and analyzed in-situ test results of an existing equipment with those of auto back equipment by appling elastic theory. As a result of the test, It has been proved that differences of tension force in the existing equipment increases with increasing the number of p.c strands. This can cause the ultimate failure of the concentrated p.c strand and the shear failure of ground. So it has been proved that auto back equipment is necessary.

• Journal of Environmental Health Sciences
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• v.42 no.2
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• pp.112-117
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• 2016

Objectives: In this study, we investigated the biodegradation rates of 8 perfluorooctanesulfonate (PFOS) alternatives synthesized at the at Changwon National University in comparison to those of PFOS potassium salt and PFOS sodium salt. Methods: A biodegradability test was performed for 28 days with microorganisms cultured in the good laboratory practice laboratory at the Korea Environment Corporation following the OECD Guidelines for the testing of chemicals, Test No. 301 C Results: While $C_5H_8F_3SO_3K$, $C_8F_{17}SO_3K$ and $C_8F_{17}SO_3Na$ were not degraded after 28 days, the 3 alternatives were biodegraded at the rates of 31.4% for $C_8H_8F_9SO_3K$, 25.6% for $C_{10}H_8F_{13}SO_3K$, 23.6% for $C_{25}F_{17}H_{32}S_3O_{13}Na_3$, 20.9% for $C_{15}F_9H_{21}S_2O_8Na_2$, 15.5% for $C_{23}F_{18}H_{28}S_2O_8Na_2$, 8.5% for $C_{17}F_9H_{25}S_2O_8Na_2$ and 4.8% for $C_6H_8F_5SO_3K$. When the concentration was the same(500 mg/L), $C_{23}F_{18}H_{28}S_2O_8Na_2$ had the lowest tension with 20.94 mN/m, which was followed by $C_{15}F_9H_{21}S_2O_8Na_2$ (23.36 mN/m), $C_{17}F_9H_{25}S_2O_8Na_2$ (27.31 mN/m), $C_{25}F_{17}H_{32}S_3O_{13}Na_3$ (28.17 mN/m), $C_{10}H_8F_{13}SO_3K$ (29.77 mN/m) and $C_8H_8F_9SO_3K$ (33.89 mN/m). Having higher surface tension of 57.64 mN/m and 67.57 mN/m, respectively, than those of the two types of PFOS salts, $C_6H_8F_5SO_3K$ and $C_5H_8F_3SO_3K$ were found valueless as substitute for PFOS. Conclusion: The biodegradation test suggest that 6 compounds could be used as substitutes for PFOS. $C_{23}F_{18}H_{28}S_2O_8Na_2$ and $C_{15}F_9H_{21}S_2O_8Na_2$ were found to be the best substitutes based on biodegradation rate and surface tension, followed by $C_{25}F_{17}H_{32}S_3O_{13}Na_3$, $C_8H_8F_9SO_3K$ and $C_{10}H_8F_{13}SO_3K$. $C_{17}F_9H_{25}S_2O_8Na_2$ was found to have relatively low value as an alternative but it still had a potential to substitute the conventional PFOS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.