• The Transactions of the Korean Institute of Power Electronics
• /
• v.19 no.5
• /
• pp.422-430
• /
• 2014

This study proposes a small-signal model and control design for a two-stage DC-DC-AC converter to investigate its dynamic characteristics in relation to battery energy storage system. When the circuit analysis of the two-stage DC-DC-AC converter is attempted simultaneously, the mathematical procedure of deriving the dynamic equation is complex and difficult. The main idea of modeling the two-stage DC-DC-AC converter states that this topology is separated into a bidirectional DC-DC converter and a single-phase inverter with an equivalent current source corresponding to that of the inverter or converter. The dynamic equations for the separated converter and inverter are then derived using the state-space averaging technique. The procedures of building the small-signal model of the two-stage DC-DC-AC converter are described in detail. Based on the derived small-signal model, the individual controllers are designed through a frequency-domain analysis. The simulation and experimental results verify the validity of the proposed modeling approach and controller design.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.3
• /
• pp.207-214
• /
• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.88-93
• /
• 2007

In this paper, a simple and improved noise parameter model of RF MOSFETs is developed and verified. Based on the analytical model of channel thermal noise, closed form expressions for four noise parameters are developed from proposed equivalent small signal circuit. The modeling results show a excellent agreement with the measured data of $0.13{\mu}m$ CMOS devices.

• Journal of Power Electronics
• /
• v.16 no.5
• /
• pp.1802-1812
• /
• 2016

Cross regulation is a key technical issue of single-inductor multiple-output (SIMO) DC-DC converters. This paper investigates the cross regulation in single-inductor dual-output (SIDO) Buck converters with continuous conduction mode (CCM) operation. The expressions of the DC voltage gain, control to the output transfer function, cross regulation transfer function, cross coupled transfer function and impedance transfer function of the converter are presented by the time averaging equivalent circuit approach. A small signal model of a SIDO CCM Buck converter is built to analyze this cross regulation. The laws of cross regulation with respect to various load conditions are investigated. Simulation and experiment results verify the theoretical analysis. This study will be helpful for converter design to reduce the cross regulation. In addition, a control strategy to reduce cross regulation is performed.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.8
• /
• pp.853-859
• /
• 2014

This study presents a technique for extracting all the extrinsic parameters of HEMTs by minimizing the residual errors between a pinch-off cold-FET's gate and drain pad de-embedded Z-parameters and its modeled Z-parameters calculated by the cold-FET's remaining parameters. The presented technique allows us to successfully extract the remaining extrinsic parameter values as well as the gate and drain pad capacitance value without the additional fabrications of the gate and drain dummy pad.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.2
• /
• pp.59-64
• /
• 2004

In this paper, a Cold PHEMT equivalent circuit was proposed, and it is applied to extract extrinsic resistances. By using the proposed Cold PHEMT equivalent circuit, the variation of impedance with frequency and bias were mainly emphasized. Especially, the convergence of impedance with frequency and the change in impedance with bias were carefully analyzed, which may be used for fast extraction of extrinsic resistances. The proposed extraction method demonstrated improving of small signal model accuracy than conventional extraction method.

• Journal of Sensor Science and Technology
• /
• v.4 no.4
• /
• pp.29-40
• /
• 1995

In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.7
• /
• pp.7-12
• /
• 2004

An improved extraction method considering ac current crowding effect is investigated to determine intrinsic ( $C_{\mu}$) and extrinsic ( $C_{\mu}$) base-collector capacitances of bipolar junction transistors separately. The drawbacks of conventional methods are pointed out, and the improved extraction equations are derived from a cutoff mode equivalent circuit with the ac crowding capacitance. The frequency response curves of modeled current and power gains using the extracted values of $C_{\mu}$ and $C_{\mu}$ have much better agreements with measured ones than those of the conventional methods, verifying the accuracy of the improved technique.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.5
• /
• pp.11-16
• /
• 2017

The frequency dependent input resistance observed in RF MOSFETs is analyzed in detail by deriving pole and zero frequency equations from a simplified input equivalent circuit. Using this theoretical analysis, we find that the reduction effect of the input resistance in the low frequency region arises from the channel resistance between source and pinch-off region in the saturation region. This channel resistance effect on the low frequency reduction of the input resistance is physically validated by performing small-signal equivalent circuit modeling with varying the channel resistance.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.37 no.11
• /
• pp.17-22
• /
• 2000

A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.