IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

  • Tanaka, Tomoki (Department of Electronic Systems Engineering, The University of Shiga Prefecture) ;
  • Kishine, Keiji (Department of Electronic Systems Engineering, The University of Shiga Prefecture) ;
  • Tsuchiya, Akira (Department of Communications and Computer Engineering, Kyoto University) ;
  • Inaba, Hiromi (Department of Electronic Systems Engineering, The University of Shiga Prefecture) ;
  • Omoto, Daichi (Department of Electronic Systems Engineering, The University of Shiga Prefecture)
  • Received : 2016.03.31
  • Accepted : 2016.06.05
  • Published : 2016.06.30
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Abstract

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

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References

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