• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.378-379
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• 2018

본 연구는 속응형 단상 UPS(Uninterruptible Power Supply)를 위한 이상전원 검출 알고리즘에 관한 연구이다. 한국전력공사 등의 특수한 UPS 응용분야에서는 전원의 1/4주기 이내에 전원의 이상을 검출하고 UPS가 정상 기동할 필요가 있다. 본 연구에서는 가상DQ기반의 고성능 PLL(Phase Locked Loop)을 응용하여 별도의 전원검출 알고리즘 없이도 임의의 위상각에서 1/4주기이내에 전원의 크기 및 위상에 관한 오류를 검출할 수 있음을 보인다. 제시된 방법은 시뮬레이션 및 실험을 통해 검증하였다.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.506-507
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• 2013

본 논문은 단상 전원 시스템에서 입력전원의 위상각 추정에 2차 일반화 적분기(Second-Order Generalized Integrator - SOGI)를 기반으로 하는 적응 필터구조를 적용한다. SOGI 출력은 전원 위상각과 관련되고, 올바른 출력을 위해서는 중심 주파수 ${\omega}^{\prime}$이 전원 주파수를 빠르게 추정할 수 있도록 FLL(Frequency Locked Loop)제어가 필요하다. SOGI-FLL의 기존의 방법과는 다르게 비선형 특성이 강한 주파수 동기화 동특성 모델에 퍼지제어를 적용함으로써 복잡한 선형화 과정이 필요하지 않으며, 실시간 이득 조절로 빠르게 전원 주파수 추정을 할 수 있는데 이는 최종적으로 빠른 전원 위상각 추정을 의미한다. 제안된 방법에 대해서 시뮬레이션을 통하여 그 타당성을 검증한다.

• Journal of Power Electronics
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• v.12 no.6
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• pp.851-858
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• 2012

This paper presents resonant inverter tuning for current source parallel resonant induction heating systems based on a new self oscillating switching technique. The phase error is suppressed in a wide range of operating frequencies in comparison with Phase Locked Loop (PLL) techniques. The proposed switching method has the capability of tuning under fast changes in the resonant frequency. According to this switching method, a multi-frequency induction heating (IH) system is proposed by using a single inverter. In comparison with multi-level inverter based IH systems, the advantages of this technique are its simple structure, better transients and wide range of operating frequencies. A laboratory prototype was built with an operating frequency of 35 kHz to 55 kHz and 300 W of output power. The performance of the IH system shows the validity of the new switching technique.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.80-82
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• 2019

태양광발전과 풍력발전으로 대표되는 분산형 전원이 계통에 연계됨에 따라 계통 사고 발생 시에 계통연계형 인버터에 대한 각국의 계통 규정(Grid code)이 더욱 엄격해 지고 있다. 최근 국외 계통 규정에서는 저 전압 사고뿐만 아니라 영 전압 사고 시에 인버터가 일정 시간 계통 연계를 유지하며 무효전류 출력 기법을 통해 계통 복구를 지원할 것을 요구하고 있다. 계통 사고 시, 사고 전압 잔존량에 따라 무효전류를 정확하게 출력하기 위해 인버터의 PLL(Phase Locked Loop) 제어는 중요하다. 그러나 이러한 PLL 제어의 동적 특성은 계통 사고 순간의 전압 강하 및 사고 위상에 따라 영향을 받게 되고 영 전압 사고에서는 위상 추종이 불가능하기 때문에 복합적인 문제가 나타난다. 본 논문에서는 영 전압 사고에서 사고 위상에 따라 각각 다르게 나타나는 PLL 동적 특성을 시뮬레이션을 통해 분석하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.199-204
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• 2010

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.