• Title/Summary/Keyword: Single Junction

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Thermal Dissipation Characteristics of Multi-Chip LED Packages (멀티 칩 LED 패키지의 방열 특성)

  • Kim, Byung-Ho;Moon, Cheol-Hee
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.25 no.12
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    • pp.34-41
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    • 2011
  • In order to understand the thermal performance of each LED chips in multi-chip LED package, a quantitative parametric analysis of the temperature evolution was investigated by thermal transient analysis. TSP (Temperature Sensitive Parameter) value was measured and the junction temperature was predicted. Thermal resistance between the p-n junction and the ambient was obtained from the structure function with the junction temperature evolution during the cooling period of LED. The results showed that, the thermal resistance of the each LED chips in 4 chip-LED package was higher than that of single chip- LED package.

Microwave plasma emission from tunnel-injected nonequilibrium high-Tc superconductors

  • Lee, Kie-Jin
    • 한국초전도학회:학술대회논문집
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    • v.10
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    • pp.9-14
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    • 2000
  • We report on the novel nonequilibrium nlicrowave emission from quasiparticle-injected high-Tc superconductors. The phenomena have been observed for the current-injected YBCO/I/Au or BSCCO/I/Au thin-film tunnel junctions and BSCCO single-crystal intrinsic Josephson mesa junction samples. For the thin-film tunnel junctions, the emitted radiation appears as broadband. For the intrinsic BSCCO mesa samples, the radiation appears as three different modes of emissions depending on the bias point in the hysteretic current-voltage characteristics; Josephson-emission, nonequilibrium broad emission and sharp coherent microwave emission. The results were interpreted by the Josephson plasma excitation model due to quasiparticle injection.

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Fabrication of p-type FinFETs with a 20 nm Gate Length using Boron Solid Phase Diffusion Process

  • Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.1
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    • pp.16-21
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    • 2006
  • A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

Characteristics of p-Cu2O/n-Si Heterojunction Photodiode made by Rapid Thermal Oxidation

  • Ismail, Raid A.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.51-54
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    • 2009
  • Transparent Cuprous oxide film was deposited by rapid thermal oxidation (RTO) of Cu at $500^{\circ}C$/45s condition on textured single-crystal n-Si substrate to form $Cu_2O$/n-Si heterojunction photodiode. The Hall effect measurements for the $Cu_2O$ films showed a p-type conductivity. The photovoltaic and electrical properties of the junction at room temperature were investigated without any post-deposition annealing. I-V characteristics revealed that the junction has good rectifying properties. The C-V data showed abrupt junction and a built-in potential of 1 V. The photodiode showed good stability and high responsivity in the visible at three regions; 525 nm, 625-700 nm, and 750nm denoted as regions A, B, and C, respectively.

A Study on Destruction Characteristics of BJT (Bipolar Junction Transistor) at Different Pulse Repetition Rate (다양한 펄스 반복률에서의 NPN BJT (Bipolar Junction Transistor)의 파괴 특성에 관한 연구)

  • Bang, Jeong-Ju;Huh, Chang-Su;Lee, Jong-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.3
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    • pp.167-171
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    • 2014
  • This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

Design for a Single-layer Feeder Waveguide Array using $\pi$-Junctions with the Inductive Wall (유도성 벽을 이용한 $\pi$ 분기형 일층구조 급전도파관 어레이의 설계)

  • 민경식;김광욱;김동철;임학규
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.2
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    • pp.257-267
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    • 2001
  • This paper presents a design for a single-layer feeder waveguide array using $\pi$-junctions with the inductive wall. The feed structure consists of a single waveguide placed on the same layer as radiating waveguide and is characterized by the unit divider, called a $\pi$-junction. This $\pi$-junction with an inductive wall splits part of the power into two branchs waveguide through one coupling window, and can excite densely arrayed waveguide at equal phase and amplitude. The power dividing characteristics of the cascade of $\pi$ -junctions are analyzed by Galerkin's method of moments. The numerical results show reasonable agreement with the experimental results. From the optimum simulation results based on the feeder waveguide using $\pi$-junction, we obtained the scattering matrices of the feeder divided power at 3.95 GHz.

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Laser patterning process for a-Si:H single junction module fabrication (레이저 가공에 의한 비정질 실리콘 박막 태양전지 모듈 제조)

  • Lee, Hae-Seok;Eo, Young-Joo;Lee, Heon-Min;Lee, Don-Hee
    • 한국신재생에너지학회:학술대회논문집
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    • 2007.11a
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    • pp.281-284
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    • 2007
  • Recently, we have developed p-i-n a-Si:H single junction thin film solar cells with RF (13.56MHz) plasma enhanced chemical vapor deposition (PECVD) system, and also successfully fabricated the mini modules ($>300cm^2$), using the laser patterning technique to form an integrated series connection. The efficiency of a mini module was 7.4% ($Area=305cm^2$, Isc=0.25A, Voc=14.74V, FF=62%). To fabricate large area modules, it is important to optimise the integrated series connection, without damaging the cell. We have newly installed the laser patterning equipment that consists of two different lasers, $SHG-YVO_4$ (${\lambda}=0.532{\mu}m$) and YAG (${\lambda}=1.064{\mu}m$). The mini-modules are formed through several scribed lines such as pattern-l (front TCO), pattern-2 (PV layers) and pattern-3 (BR/back contact). However, in the case of pattern-3, a high-energy part of laser shot damaged the textured surface of the front TCO, so that the resistance between the each cells decreases due to an incomplete isolation. In this study, the re-deposition of SnOx from the front TCO, Zn (BR layer) and Al (back contact) on the sidewalls of pattern-3 scribed lines was observed. Moreover, re-crystallization of a-Si:H layers due to thermal damage by laser patterning was evaluated. These cause an increase of a leakage current, result in a low efficiency of module. To optimize a-Si:H single junction thin film modules, a laser beam profile was changed, and its effect on isolation of scribed lines is discussed in this paper.

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Simulation and Layout of Single Flux Quantum AND gate (단자속 양자 AND gate의 시뮬레이션과 Layout)

  • 정구락;박종혁;임해용;강준희;한택상
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2002.02a
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    • pp.141-143
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    • 2002
  • We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

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