• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제35회 하계학술대회 초록집
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• pp.48-48
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• 2008

• 조명전기설비학회논문지
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• 제25권12호
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• pp.34-41
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• 2011

In order to understand the thermal performance of each LED chips in multi-chip LED package, a quantitative parametric analysis of the temperature evolution was investigated by thermal transient analysis. TSP (Temperature Sensitive Parameter) value was measured and the junction temperature was predicted. Thermal resistance between the p-n junction and the ambient was obtained from the structure function with the junction temperature evolution during the cooling period of LED. The results showed that, the thermal resistance of the each LED chips in 4 chip-LED package was higher than that of single chip- LED package.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.9-14
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• 2000

We report on the novel nonequilibrium nlicrowave emission from quasiparticle-injected high-Tc superconductors. The phenomena have been observed for the current-injected YBCO/I/Au or BSCCO/I/Au thin-film tunnel junctions and BSCCO single-crystal intrinsic Josephson mesa junction samples. For the thin-film tunnel junctions, the emitted radiation appears as broadband. For the intrinsic BSCCO mesa samples, the radiation appears as three different modes of emissions depending on the bias point in the hysteretic current-voltage characteristics; Josephson-emission, nonequilibrium broad emission and sharp coherent microwave emission. The results were interpreted by the Josephson plasma excitation model due to quasiparticle injection.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.51-54
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• 2009

Transparent Cuprous oxide film was deposited by rapid thermal oxidation (RTO) of Cu at $500^{\circ}C$/45s condition on textured single-crystal n-Si substrate to form $Cu_2O$/n-Si heterojunction photodiode. The Hall effect measurements for the $Cu_2O$ films showed a p-type conductivity. The photovoltaic and electrical properties of the junction at room temperature were investigated without any post-deposition annealing. I-V characteristics revealed that the junction has good rectifying properties. The C-V data showed abrupt junction and a built-in potential of 1 V. The photodiode showed good stability and high responsivity in the visible at three regions; 525 nm, 625-700 nm, and 750nm denoted as regions A, B, and C, respectively.

• 한국전기전자재료학회논문지
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• 제27권3호
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• pp.167-171
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• 2014

This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

• 한국전자파학회논문지
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• 제12권2호
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• pp.257-267
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• 2001

본 논문은 유도성 벽을 이용한 $\pi$분기형 일층구조 급전도파관 어레이 설계에 대하여 기술하고 있다. 이 구조는 복사도파관과 급전도파관을 같은 층에 위치시킴으로써 전체 구조를 일층구조로 만들었으며, 유도성 벽을 이용함으로써 하나의 도파관 창으로부터 복사도파관으로 급전부의 전력분배를 동위상. 동진폭으로 분배되도록 설계하였다. Galerkin's 모멘트법을 이용하여 유동성 벽을 포함한 다단성 급전도파관을 엄밀하게 해석하였고, 설계에 있어서 전송선로형 등가회로 기념을 이용하여 전력분배비와 반사계수를 구하였다. $\pi$결합분기기 한 단에 대해 시뮬레이션하고 그 값을 토대로 하여 실제 제작을 통해 그 타당성을 입증하였고, 한 단에 대한 설계 방법을 토대로 반복 계산에 의한 설계 주파수 3.95GHz을 중심으로 하는 8-port 어레이 급전구조를 설계하였다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.281-284
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• 2007

Recently, we have developed p-i-n a-Si:H single junction thin film solar cells with RF (13.56MHz) plasma enhanced chemical vapor deposition (PECVD) system, and also successfully fabricated the mini modules ($>300cm^2$), using the laser patterning technique to form an integrated series connection. The efficiency of a mini module was 7.4% ($Area=305cm^2$, Isc=0.25A, Voc=14.74V, FF=62%). To fabricate large area modules, it is important to optimise the integrated series connection, without damaging the cell. We have newly installed the laser patterning equipment that consists of two different lasers, $SHG-YVO_4$ (${\lambda}=0.532{\mu}m$) and YAG (${\lambda}=1.064{\mu}m$). The mini-modules are formed through several scribed lines such as pattern-l (front TCO), pattern-2 (PV layers) and pattern-3 (BR/back contact). However, in the case of pattern-3, a high-energy part of laser shot damaged the textured surface of the front TCO, so that the resistance between the each cells decreases due to an incomplete isolation. In this study, the re-deposition of SnOx from the front TCO, Zn (BR layer) and Al (back contact) on the sidewalls of pattern-3 scribed lines was observed. Moreover, re-crystallization of a-Si:H layers due to thermal damage by laser patterning was evaluated. These cause an increase of a leakage current, result in a low efficiency of module. To optimize a-Si:H single junction thin film modules, a laser beam profile was changed, and its effect on isolation of scribed lines is discussed in this paper.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.141-143
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• 2002

We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.48-48
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• 2001