• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.31-36
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• 2004

we developed a technique to manufacture more reliable polycrystalline silicon TFT-LCDs using UV cleaning and buffered oxide etch(BOE) cleaning which remove the native oxide of the silicon surface before laser annealing. To investigate the effects of pre-treatments on the surface roughness of polycrystalline silicon, we measured atomic force microscopy(AFM). Also the electrical characteristics of polysilicon TFTs, breakdown characteristic and switching Performance, were tested for various pre-treatment conditions and several locations in large glass substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Journal of the Korean Ceramic Society
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• v.28 no.11
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• pp.859-864
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• 1991

High quality lead titanate thin films were fabricated by spin coating on a silicon substrate. The resulting dried gel layers were uniform in thickness through 2$\times$2 $\textrm{cm}^2$ area, and polycrystalline perovskite structures developed almost crack free with a heat treatment above 50$0^{\circ}C$ in films with thickness above 360 nm. Metastable pyrochlore structures were observed in films with thickness of 160 nm when heat treated at 500 and $600^{\circ}C$, but these structure did not appear in films with thickness of 360 nm. The thickness dependence in crystal structure of films was studied. by varying the substrate condition and analyzing the interface between the film and substrate. In native oxide films on silicon stbstrates, amorphous dried gel layers were heterogeneously nucleated. Metastable cubic pyrochlore structure could be crystallized in amorphous native oxide.

• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.310-316
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1{\mu}m$ in coating thickness. AISI 52100 steel ball was used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction (XRD). Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and sliding tests.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.6
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• pp.401-405
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• 2017

Because silicon thin film solar cells have a high absorption coefficient in visible light, they can absorb 90% of the solar spectrum in a $1-{\mu}m$-thick layer. Silicon thin film solar cells also have high transparency and are lightweight. Therefore, they can be used for building integrated photovoltaic (BIPV) systems. However, the contact electrode needs to be replaced for fabricating silicon thin film solar cells in BIPV systems, because most of the silicon thin film solar cells use metal electrodes that have a high reflectivity and low transmittance. In this study, we replace the conventional aluminum top electrode with a transparent aluminum-doped zinc oxide (AZO) electrode, the band level of which matches well with that of the intrinsic layer of the silicon thin film solar cell and has high transmittance. We show that the AZO effectively replaces the top metal electrode and the bottom fluorine-doped tin oxide (FTO) substrate without a noticeable degradation of the photovoltaic characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• Journal of the Optical Society of Korea
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• v.15 no.1
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• pp.1-3
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• 2011

We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.