• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2221-2225
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• 2007

Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.713-717
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• 2004

In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.727-730
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• 2003

Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5${\mu}{\textrm}{m}$width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.

• Journal of information and communication convergence engineering
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• v.1 no.2
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• pp.67-69
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• 2003

The experimental studies for the etch properties of the oxide grown on silicon substrate, which is in diluted hydrogen fluoride (HF) solution, are presented. Using different ion implantation dosages, dopants and energies, silicon substrate was implanted. The wet etching in diluted HF solution is used as a mean of wafer cleaning at various steps of VLSI processing. It is shown that the wet etch rate of oxide grown on various implanted silicon substrates is a strong function of ion implantation dopants, dosages and energies. This phenomenon has never been reported before. This paper shows that the difference of wet etch rate of oxide by ion implantation conditions is attributed to the kinds and volumes of dopants which was diffused out into $SiO_2$ from implanted silicon during thermal oxidation.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.79-83
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• 2009

In this study, the characteristics of amorphous silicon etching for the formation of gate electrodes have been evaluated at the variation of several process parameters. When total flow rates composed of $Cl_2/HBr/O_2$ gas mixtures increased, the etch rate of amorphous silicon layer increased, but critical dimension (CD) bias was not notably changed regardless of total flow rate. As the amount of HBr in the mixture gas became larger, amorphous silicon etch rate was reduced by the low reactivity of Br species. In the case of increasing oxygen flow rate, etch selectivity was increased due to the reduction of oxide etch rate, enhancing the stability of silicon gate etching process. However, gate electrodes became more sloped according to the increase of oxygen flow rate. Higher source power induced the increase of amorphous silicon etch rate and CD bias, and higher bias power had a tendency to increase the etch rate of amorphous silicon and oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.02a
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• pp.106-106
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• 2002