• The Korean Journal of Pain
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• v.7 no.2
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• pp.222-230
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• 1994

Acupuncture-like transcutaneous electrical nerve stimulation(ALTENS) on acupuncture site(dorsal and ventral side of finger) were compared with a placebo site(forearm) by infrared thermal imaging. Six disease-free volunteers underwent, on different days, an ALTENS treatment and a placebo treatment in a cross-over sequences of stimulation control and inhibition control in excess of 50 treatments. ALTENS treatments were given at 30Hz at an intensity just below pain threshold delivered to acupuncture points on fingers. Placebo stimulations were administered in similar manner. After every thirty minutes of ALTENS and placebo treatment with stimulation, inhibition control sequence and vice versa, we examined whole body infrared thermal imaging and checked changed skin temperature on frontal, anterior chest, upper and lower abdomen, dorsal and ventral aspect of hand, thoracic and lumbar area, anterior and posterior aspect of lower leg. There were significant skin temperature elevations with ALTENS treatment, especially finger control gate corresponding organ area. Placebo treatment revealed no skin temperature change. We concluded that ALTENS on finger control gate influence physiologic state as opposed to conventional electric stimulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.326-332
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• 2017

A switched VCO-based UWB transmitter for 3-5 GHz is implemented using $0.18{\mu}m$ CMOS technology. Using RF switch and timing control of DPGs, the uniform RF power and low power consumption are possible regardless of carrier frequency. And gate control of RF switch enables the undesired side lobe rejection sufficiently. The measured pulse width is tunable from 0.5 to 2 ns. The measured energy efficiency per pulse is 4.08% and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.214-220
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• 2012

About 12 million people of the mobility handicapped were increased by the end of 2009 year. Universal design concept has been implemented in developed countries. Since 2004 low-floor buses are in Korea. In this study, there is no provision for mobility handicapped and small buses that can be comfortable riding car ramp design presented. The gate of a small buses lowered height of 200mm. Install the ramp in the center of the ramp by an air cylinder moves from side to side. The slope of the ramp was controlled by a hinge. Air cylinder thin type applicable in the narrow space of the slide cylinder was used.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.806-808
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• 1992

This paper describes a buried-island SOI MOSFET structure which can reduce the edge channel effect by improving the interface properties at the side wall of active island and by reducing the strength of electric field applied at the upper corner of the side wall from the gate. Also, the buried-island SOl structure can obtain the uniform thickness of SOl film. The buried-island structure can be achieved by Zone- Melting-Recrystallization of polysilicon and polishing. Both simulated and experimental results show that the buried-island SOl NMOSFET has less edge channel effect than the conventional SOl NMOSFET using LOCOS or mesa isolation technique.

• Journal of architectural history
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• v.6 no.3 s.13
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• pp.23-44
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• 1997

There are two main halls in the Main Palace of the Koryo Dyansty in the 11th and 12th century. One, named Hoekyongjeon, was served only for special ceremony ; hundred Buddhist priests' sermons or receiption of Chinese emperor's letters. The other one, Kondukjeon, was used as ordinary throne hall. The ordinary throne hall was built when the palace was erected at the beginning era of the Koryo Danasty, while the special ceremony hall built after the reconstruction in the 11th century. The throne hall was located at northwest side of the special ceremony hall. Audience chamber and King's bedroom were located at west and northwest side of the throne hall. The basic layout of the Palace showed unsymmetrical shape. It seemed mainly effected by its undulating terraine. The acess road from main gate to the throne hall showed zigzag way, by following a stream penetrating the site obliquely, It could be said that the Main Palace of the Koryo Danasty achieved its originality on the aspect of unsymmetrical layout and zigzag acess road, which was not found in the former palaces.

• Journal of Power Electronics
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• v.17 no.2
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• pp.570-578
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• 2017

This paper proposes a method to stabilize the output voltage of the secondary side of an Inductive Power Transfer (IPT) system through tuning/detuning via a serial tuned DC Voltage-controlled Variable Capacitor (DVVC). The equivalent capacitance of the DVVC changes with the conduction period of a diode in the DVVC controlled by DC voltage. The output voltage of an IPT system can be made constant when this DVVC is used as a variable resonant capacitor combined with a PI controller generating DC control voltage according to the fluctuations of the output voltage. Since a passive diode instead of an active switch is used in the DVVC, there are no active switch driving problems such as a separate voltage source or gate drivers, which makes the DVVC especially advantageous when used at the secondary side of an IPT system. Moreover, since the equivalent capacitance of the DVVC can be controlled smoothly with a DC voltage and the passive diode generates less EMI than active switches, the DVVC has the potential to be used at much higher frequencies than traditional switch mode capacitors.

• Journal of Korea Foundry Society
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• v.32 no.2
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• pp.65-74
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• 2012

In this paper, we present the results of our studies on optimal die design towards development of a vacuum die casting process to fabricate fuel cell bipolar plate with micro-channel array. Cavity and overflow shape is designed by computational filling analysis of MAGMA soft. Optimal die design consists of seven overflows at the end of cavity and three overflows at each side wall of cavity. The molten metal that passed the gate and reached the side wall flowed into the side overflow, no turbulent flow occurred, and the filling behavior and velocity distribution were uniform. In addition, partially solidified molten metal passing through the channel was perfectly eliminated by overflow without back-flow. When vacuum pressure, injection speed of low and high region was 300 mbar, 0.3 m/s and 2.5 m/s respectively with Silafont 36 die casting alloy, sound sample without casting defects was obtained. The experimental results are nearly consistent with simulation results.

• Journal of Power Electronics
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• v.11 no.3
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.