• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.453-456
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• 1998

The electrical properties of $Si_{1-x}Ge_{x}$ samples have been investigated. The sample structures were grown by MBE (molecular geam epitaxy) with Ge mole-fraction of x=0.0, x=0.05, x=0.1, and x=0.2. To examine the influence of the thermal processing, the $O_{2}$ and N$_{2}$ process were performed at 800[.deg. C] and 900[.deg. C], respectively. After this thermal process, hall measurements have been done over a wide range of the ambient temperature between 320[.deg. K] and 10[.deg. K] to find the temperature dependence using the comparessed-He gas system. The Ge-rich layer has been formed at the $SiO_{2}$/SiGe interface and it has an effect on the hall mobility. And it has been found that hall mobility was increased by the $N_{2}$ annealing process comparing with dry oxidation process at both 800[.deg.C] and900[.deg. C].

• Korean Journal of Materials Research
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• v.4 no.8
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• pp.895-905
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• 1994

The solid phase crystallization behavior of undoped amorphous $Si_{1-x}Ge_{x}$ (X=O to 0.53) alloyfilms was studied by X-ray diffractometry(XRD) and transmission electron microscopy(TEM). Thefilms were deposited on thermally oxidized 5" (100) Si wafer by MBE(Mo1ecular Beam Epitaxy) at 300'C and annealed in the temperature range of $500^{\circ}C$ ~ $625^{\circ}C$. From XRD results, it was found that the thermal budget for full crystallization of the film is significantly reduced as the Ge concentration in thefilm is increased. In addition, the results also shows that pure amorphous Si film crystallizes with astrong (111) texture while the $Si_{1-x}Ge_{x}$ alloy film crystallzes with a (311) texture suggesting that the solidphase crystallization mechanism is changed by the incorporation of Ge. TEM analysis of the crystallized filmshow that the grain morphology of the pure Si is an elliptical and/or a dendrite shape with high density ofcrystalline defects in the grains while that of the $Si_{0.47}Ge_{0.53}$ alloy is more or less equiaxed shape with muchlower density of defects. From these results, we conclude that the crystallization mechanism changes fromtwin-assisted growth mode to random growth mode as the Ge cocentration is increased.ocentration is increased.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Journal of the Korean Vacuum Society
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• v.6 no.S1
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• pp.47-52
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• 1997

Metastable pseudomorphic GeSi layers grown by vapor phase epitaxy on Si(100) substrates were implanted at room temperature. The implantations were performed with 90 KeV As ions to a dose of $1\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.08}Si_{0.92}$ layers and 709 keV $BF_2^+$ ions to a dose of $3\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.06}Si_{0.94}$layers. The samples were subsequently annealed for short 10-40 s durations in a lamp furnace with a nitrogen ambient or for a long 30 min period in a vacuum tube furnace. For $Ge_{0.08}Si_{0.92}$samples annealed for a 30 min-longt duration at $700^{\circ}C$ the dopant activation can only reach 50% without introducing significant strain relaxaion whereas samples annealed for short 40s periods (at $850^{\circ}C$) can achieve more than 90% activation without a loss of strain, For $Ge_{0.06}Si_{0.94}$samples annealed for either 40s or 30min at $800^{\circ}C$ full electrical activation of the boron is exhibited in the GeSi epilayer without losing their strain. However when annealed at $900^{\circ}C$ the strain in both implanted and unimplanted layers is partly relaxed after 30min whereas it is not visibly relaxed after 40s.

• Journal of the Korean Vacuum Society
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• v.8 no.2
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• pp.148-152
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• 1999

the low temperature magnetoresistance effect, electron mobilities, and 2 Dimensional electron Gases (2DEG) properties were investigated in $Si/Si_{1-x}Ge_x$ quantum well devices. N-type $Si/Si_{1-x}Ge_x$ structures were fabricated by utilizing a gas source Molecular Beam Epitaxy (GSMBE). Thermal oxidation was carried out in a dry O atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by using a Hall effect and a magnetoresistant effect at low temperatures down to 0.4K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2DEG) in s tensile strained Si quantum well. The electron sheet density (ns) of $1.5\times10^{12}[\textrm{cm}^{-2}]$ and corresponding electron mobility of 14200 $[\textrm{cm}^2V^{-1}s^{-1}]$ were obtained at a low temperature of 0.4K from $Si/Si_{1-x}Ge_x$ structures with thermally grown oxides.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.657-662
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• 2003

This paper presents a new fabrication method of selective SiGe epitaxial growth at 650 $^{\circ}C$ on (100) silicon wafer with oxide patterns by reduced pressure chemical vapor deposition. The new method is characterized by a cyclic process, which is composed of two parts: initially, selective SiGe epitaxy layer is grown on exposed bare silicon during a short incubation time by SiH$_4$/GeH$_4$/HCl/H$_2$system and followed etching step is achieved to remove the SiGe nuclei on oxide by HCl/H$_2$system without source gas flow. As a result, we noted that the addition of HCl serves not only to reduce the growth rate on bare Si, but also to suppress the nucleation on SiO$_2$. In addition, we confirmed that the incubation period is regenerated after etching step, so it is possible to grow thick SiGe epitaxial layer sustaining the selectivity. The effect of the addition of HCl and dopants incorporation was investigated.