• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.453-456
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• 1998

The electrical properties of $Si_{1-x}Ge_{x}$ samples have been investigated. The sample structures were grown by MBE (molecular geam epitaxy) with Ge mole-fraction of x=0.0, x=0.05, x=0.1, and x=0.2. To examine the influence of the thermal processing, the $O_{2}$ and N$_{2}$ process were performed at 800[.deg. C] and 900[.deg. C], respectively. After this thermal process, hall measurements have been done over a wide range of the ambient temperature between 320[.deg. K] and 10[.deg. K] to find the temperature dependence using the comparessed-He gas system. The Ge-rich layer has been formed at the $SiO_{2}$/SiGe interface and it has an effect on the hall mobility. And it has been found that hall mobility was increased by the $N_{2}$ annealing process comparing with dry oxidation process at both 800[.deg.C] and900[.deg. C].

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.378.2-378.2
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• 2014

We have investigated optical characteristics of $p-Ge_{0.99}Sn_{0.01}$ and Ge films grown on Si substrates using photoreflectance (PR) spectroscopy. The $Ge_{0.99}Sn_{0.01}$ and Ge films were grown by using an ultra-high vacuum chemical vapor deposition and molecular beam epitaxy methods, respectively. PR spectra were measured at 25 K and an extended InGaAs detector was used. By comparing $Ge_{0.99}Sn_{0.01}/Si$ and Ge/Si spectra, we observed the signals related to direct transition and split-off band of $Ge_{0.99}Sn_{0.01}$. The transition energies of $Ge_{0.99}Sn_{0.01}$ and Ge films were approximately 0.74 and 0.84 eV, respectively. Considering the shift of split-off band transition of $Ge_{0.99}Sn_{0.01}$, we suppose that the transition at 0.74 eV is attributed to direct transition between ${\Gamma}$ band and valence band. The temperature- and excitation power-dependent PR spectra were also measured.

• 한국산학기술학회논문지
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• 제5권4호
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• pp.367-370
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• 2004

초고속 RF IC의 핵심소자인 SiGe 에피텍시층을 가진 이종양극트란지스터(hetero junction bipolar transistor: HBT)를 0.35㎛급 Si-Ge BiCMOS공정으로 제작하였다. 낮은 VBE영역에서의 current gain의 선형성을 향상시키기 위하여 SiGe에피텍시층의 결함밀도를 감소시킬 수 있는 캐핑실리콘의 두께와 EDR온도의 최적화 공정조건을 알아보았다. 캐핑 실리콘의 두께를 200Å과 300Å으로 나누고 초고속 무선통신에서 요구되는 낮은 노이즈를 위한 EDR(Emitter Drive-in RTA)의 온도와 시간을 900-1000℃, 0-30 sec로 각각 변화시키면서 최적조건을 확인하였다. 실험범위 내에서의 최적공정조건은 300Å의 capping 실리콘과 975℃-30sec의 EDR 조건을 확인하였다.

• 한국결정성장학회지
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• 제9권2호
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• pp.207-211
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• 1999

가스원 분자선 에피택시(GS-MBE)로 성장시킨 $Si/Si_{1-x}Ge_x$ MODFET의 미세조직을 투과식 전자현미경과 간섭광학현미경을 이용하여 관찰하였다. 증착온도변화에 따른 불일치전위의 분포에 큰 변화는 없었지만, 증착온도가 높을수록 표면조도가 거칠어졌고 표면 결함이 나타났다. Si 전기활성층 근처에서는 조성경사기능층보다 전위밀도가 상당히 낮았다. 결정성장 온도를 낮춤에 따라 전기이동도는 증가하였다.

• 한국진공학회지
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• 제6권S1호
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• pp.47-52
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• 1997

Metastable pseudomorphic GeSi layers grown by vapor phase epitaxy on Si(100) substrates were implanted at room temperature. The implantations were performed with 90 KeV As ions to a dose of $1\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.08}Si_{0.92}$ layers and 709 keV $BF_2^+$ ions to a dose of $3\times 10^{13}\;\textrm{cm}^2$ for $Ge_{0.06}Si_{0.94}$layers. The samples were subsequently annealed for short 10-40 s durations in a lamp furnace with a nitrogen ambient or for a long 30 min period in a vacuum tube furnace. For $Ge_{0.08}Si_{0.92}$samples annealed for a 30 min-longt duration at $700^{\circ}C$ the dopant activation can only reach 50% without introducing significant strain relaxaion whereas samples annealed for short 40s periods (at $850^{\circ}C$) can achieve more than 90% activation without a loss of strain, For $Ge_{0.06}Si_{0.94}$samples annealed for either 40s or 30min at $800^{\circ}C$ full electrical activation of the boron is exhibited in the GeSi epilayer without losing their strain. However when annealed at $900^{\circ}C$ the strain in both implanted and unimplanted layers is partly relaxed after 30min whereas it is not visibly relaxed after 40s.

• 한국전기전자재료학회논문지
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• 제16권8호
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• pp.657-662
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• 2003

This paper presents a new fabrication method of selective SiGe epitaxial growth at 650 $^{\circ}C$ on (100) silicon wafer with oxide patterns by reduced pressure chemical vapor deposition. The new method is characterized by a cyclic process, which is composed of two parts: initially, selective SiGe epitaxy layer is grown on exposed bare silicon during a short incubation time by SiH$_4$/GeH$_4$/HCl/H$_2$system and followed etching step is achieved to remove the SiGe nuclei on oxide by HCl/H$_2$system without source gas flow. As a result, we noted that the addition of HCl serves not only to reduce the growth rate on bare Si, but also to suppress the nucleation on SiO$_2$. In addition, we confirmed that the incubation period is regenerated after etching step, so it is possible to grow thick SiGe epitaxial layer sustaining the selectivity. The effect of the addition of HCl and dopants incorporation was investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• 한국자기학회지
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• 제19권3호
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• pp.85-88
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• 2009

다결정 $Ge_{1-x}Mn_x$ 박막의 자기적 상들에 관한 연구가 이루어졌다. Molecular beam epitaxy(MBE) 장비를 이용해 $400^{\circ}C$ 에서 $Ge_{1-x}Mn_x$ 박막을 성장시켰다. $Ge_{1-x}Mn_x$ 박막의 캐리어 유형은 P타입 이였고, 전기 비저항 값은 $4.0{\times}10^{-2}{\sim}1.5{\times}10^{-4}ohm-cm$이었다. 자기적인 특성과 미세구조의 분석에 기초하여 $Ge_{1-x}Mn_x/SiO_2$/Si(100) 박막에 310 K 이내의 큐리에온도를 지닌 강자성의 $Ge_3Mn_5$ 상이 형성되었음을 알 수 있었다. 게다가, $Ge_3Mn_5$ 상이 형성된 $Ge_{1-x}Mn_x$ 박막은 20 K, 9 T의 자기장에서 약 9%의 음의 자기저항을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.54-58
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• 1994

H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.