• Tribology and Lubricants
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• v.17 no.3
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• pp.191-197
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• 2001

Nano adhesion and friction characteristics between SPM(scanning electron microscope) tips and flat plates of different materials were experimentally studied. Tests were performed to measure adhesion and friction in AFM(atomic force microscope) and LFM(lateral force microscope) modes in different conditions of relative humidity. Three different Si$_3$N$_4$ tips (rdaii : 15nm, 22nm and 50 nm) and three different flat plates of Si-wafer(100), W-DLC(tungsten-incorporated diamond-like carbon) and DLC were used. Results generally showed that adhesion and friction increased with the tip radius, and W-DLC and DLC surfaces were superior to Si-wafer. But the adhesion force of Si-wafer showed non linearity with the tip radius while W-DLC and DLC surfaces showed good correlation to the “JKR model”. It was found that high adhesion force between Si-wafer and a large radius of tip was caused by a capillary action due to the condensed water.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.

• Journal of Powder Materials
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• v.23 no.1
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• pp.43-48
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• 2016

Waste SiC powders obtained from silicon wafer sludge have very low density and a narrow particle size distribution of $10-20{\mu}m$. A scarce yield of C and Si is expected when SiC powders are incorporated into the Fe melt without briquetting. Here, the briquetting variables of the SiC powders are studied as a function of the sintering temperature, pressure, and type and contents of the binders to improve the yield. It is experimentally confirmed that Si and C from the sintered briquette can be incorporated effectively into the Fe melt when the waste SiC powders milled for 30 min with 20 wt.% Fe binder are sintered at $1100^{\circ}C$ upon compaction using a pressure of 250 MPa. XRF-WDS analysis shows that an yield of about 90% is obtained when the SiC briquette is kept in the Fe melt at $1650^{\circ}C$ for more than 1 h.

• Korean Journal of Materials Research
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• v.14 no.5
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• Korean Journal of Materials Research
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• v.12 no.2
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.239-241
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• 2009

DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

• Journal of Korea Foundry Society
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• v.20 no.3
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• pp.188-196
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• 2000

A vacuum casting was proposed as a new fabrication method of Si wafer for solar cell substrate. It was tried to fabricate a Si plate with good properties and to reduce the production cost by direct vacuum casting. By $5{\sim}10$ cmHg of pressure difference Si plate with $50{\times}46{\times}1.5\;mm^3$ was fabricated. For the preventing of the reaction between graphite mold and Si melt, BN powder coating or BN insert were used. The Si wafer was poly crystalline with 100 ${\mu}m{\sim}1$ mm order of grain size. And there were some twins and dislocations in the grains.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.41-46
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• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• Journal of the Korean Society for Precision Engineering
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• v.34 no.2
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• pp.107-114
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• 2017

In this investigation, we describe a metrological technique for surface and thickness profiles of a silicon (Si) wafer by using a 6 degree of freedom (DOF) stitching method. Low coherence scanning interferometry employing near infrared light, partially transparent to a Si wafer, is adopted to simultaneously measure the surface and thickness profiles of the wafer. For the large field of view, a stitching method of the sub-aperture measurement is added to the measurement system; also, 6 DOF parameters, including the lateral positioning errors and the rotational error, are considered. In the experiment, surface profiles of a double-sided polished wafer with a 100 mm diameter were measured with the sub-aperture of an 18 mm diameter at $10\times10$ locations and the surface profiles of both sides were stitched with the sub-aperture maps. As a result, the nominal thickness of the wafer was $483.2{\mu}m$ and the calculated PV values of both surfaces were $16.57{\mu}m$ and $17.12{\mu}m$, respectively.