• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.7
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• pp.521-524
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• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• Journal of the Korean Vacuum Society
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• v.5 no.2
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• Korean Journal of Materials Research
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• v.10 no.2
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• pp.124-127
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• 2000

A new triode type Ti-silicided Si FEA(field emitter array) was realized by Ti-silicidation of Ti coated Si FEA and its field emission properties were investigated. In the fabricated device, the field emission properties through the unit pixel with $200{\mu\textrm{m}}{\times}200{$\mu\textrm{m}}$ tip array in the area of $1000{\mu\textrm{m}}{\times}1000{$\mu\textrm{m}}$ were as follows : the turn-on voltage was about 70V under high vacuum condition of $10^8Torr$, and the field emission current and steady state current degradation were about 2nA/tip and 0.3%/min under the bias of $V_A=500V\;and\;V_G=150V$. The low turn-on voltage and the high current stability during long term operation of the Ti silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.301-304
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• 2000

A new triode type Co-silicided Si FEA(field emitter array) was realized by Co-silicidation of Co coated Si FEA and its field emission properties were investigated. The field emission properties of the fabricated device through the unit pixel with $45{\times}45$ tip array in the area of $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$ under high vacuum condition of $10^{-8}Torr$ were as follows : the turn-on voltage was about 35V and the anode current was about $1.2\mu\textrm{A}(0.6㎁/tip)$ at the bias of $V_A=500V\;and\; V_G=55V$. The fabricated device showed the stable electrical characteristics without degradation of field emission current for the long term operation except for the initial transient state. The low turn-on voltage and the high current stability of the Co-silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.124-128
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• 1995

We have fabricated the vacuum magnetic device with a lateral field emitter arrays constructed on n-Si wafer, and investigated its magnetic characteristics. The device is consited to tip-arrayed emitter. gate and split-anode, The fabricated vacuum magnetic device has showed a good linearity of magnetic field and a high sensitivity compared with the conventional semiconductor magnetic device.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.8
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• pp.577-579
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• 1999

DLC film remaining on device surface could be removed by eliminating AI sacrificial layer as a final step of lift-off process in the fabrication of DLC-coated Si-tip FEA. The field emission properties(I-V curves, hysteresis, and current fluctuation etc.) of the processed device were analyzed and the process was employed to 1.76 inch-sized FEA panel fabrication in order to evaluate its FED applicability.

• ETRI Journal
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• v.24 no.4
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• pp.290-298
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• 2002

We present, for the first time, a prototype active-matrix field emission display (AMFED) in which an amorphous silicon thin-film transistor (a-Si TFT) and a molybdenum-tip field emitter array (Mo-tip FEA) were monolithically integrated on a glass substrate for a novel active-matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low-voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a-Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a-Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for $n^+-doped$ a-Si etching with high etch selectivity to intrinsic a-Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a-Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a-Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low-voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.