• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.301-307
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• 2002

Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.883-888
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm$^2$to 15.5 kgf/cm$^2$.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3313-3315
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• 1999

Si direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera respectively. A bond characteristic on the interface was analyzed by using IT- IR. Si-F bonds on Si surface after HF pre-treatment are replaced by Si-OH during a DI water rinse. Consequently, hydrophobic wafer was bonded by hydrogen bonding of Si $OH{\cdots}(HOH{\cdots}HOH{\cdots}HOH){\cdots}OH-Si$. The bond strength depends on the HF pre-treatment condition before pre- bonding (Min:$2.4kgf/crn^2{\sim}Max:14.9kgf/crn^2$)

• Korean Journal of Materials Research
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• v.8 no.10
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• pp.890-897
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• 1998

The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.47-51
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• 2000

A modified direct bonding technique employing a wet chemical deposition of $SiO_2$ film on a wafer surface to be bonded is proposed for the fabrication of Si-$SiO_2$-Si structures. Structural and electrical quality of the bonded wafers is studied. Satisfied insulating properties of interfacial $SiO_2$ layers are demonstrated. Elastic strain caused by surface morphology is investigated. The diminution of strain in the grooved structures is semi-quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

• Korean Journal of Materials Research
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• v.14 no.5
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• Korean Journal of Materials Research
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• v.11 no.3
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• pp.159-163
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• 2001

The success of SDB (silicon wafer direct bonding) technology can be estabilished by bonding on the bonded interface with no defects and Preventing temperature dependent bubbles. In this research, we observed the behavior of the intrinsic bubbles by transmitting the infrared light and the increase of the bubble pressure was found. And, the $SiO_2$-$SiO_2$ bonded wafer was achieved, which generates no intrinsic bubbles in the annealing under the atmospheric pressure. The intrinsic bubbles in the $SiO_2$-$SiO_2$ bonded wafer were generated in the annealing in the ultra high vacuum. This experimental result shows the relation between the bubble growth and the pressure.