• Journal of Powder Materials
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• v.6 no.1
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• pp.18-35
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• 1999

Phase equilibria in the system Si3N4-TiC-TiCxN1-x-C-N were determined by thermodynamic calculations (CALPHAD-method). The reaction peaction paths for Si3N4-TiC and SiC-TiC composites in the Ti-Si-C-n system were simulated at I bar N2-pressure and varying terpreatures. At a temperature of 1923 K two tie-triangles (TiC0.34N0.66+SiC+C and TiC0.13N0.87+SiC+Si3N4) and two 2-phase fieds (TiCxN1-x+SiC; 0.13

• Korean Journal of Materials Research
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• v.14 no.8
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• pp.573-578
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• 2004

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared $NiCoSi_x$ silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of $NiCoSi_x$ layers. We dry etched the photoresist/SiO/silicide/silicon patterns with $CF_4\;and\;CHF_3$ gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched $0\sim316{\AA}$ during over etch time of 3min, while silicon layers with proposed $NiCoSi_x$ silicide were not etched and showed stable surfaces. Our result implies that new $NiCoSi_x$ silicides may replace the conventional silicides due to contact etch process compatibility.

• Journal of Surface Science and Engineering
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• v.47 no.6
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• pp.354-361
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• 2014

In order to utilize silicon carbide (SiC) as an inner part of fluidized bed reactor (FBR) for manufacturing poly-silicon, we have carried out the thermodynamic calculation on the overall reactions including poly-silicon synthesis and compatibility of SiC with FBR process. The resources of silicon included $SiH_4(MS)$, $SiHCl_3(TCS)$ and $SiCl_4(STC)$ and the thermodynamic yield of the FBR with MS, TCS and STC were compared each other with variable range of temperature, pressure and hydrogen to silicon ratio. The silicon yield of MS, TCS and STC were 100%, 28% and 4%, respectively, throughout the conventional FBR conditions. Silicon carbide having high hardness and strength showed strong resistance to granule collisions during the FBR process using a lab-scale reactor. And it also showed quite good compatibility with the typical FBR processes of MS and TCS resources.

• Proceedings of the Korean Nuclear Society Conference
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• 2001.05a
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• pp.272.2-272
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• 2001

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.533-536
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• 2006

VIATRON TECHNOLOGIES has developed Field-Enhanced Rapid Thermal Processor (FERTP) system that enables LTPS LCD and AMOLED manufacturers to produce poly-Si films at low cost, high throughput, and high yield. The FE-RTP allows the diverse process options including crystallization, thermal oxidation of gate oxides and fast pre-compactions. The process and equipment compatibility with a-Si TFT lines is able to provide a viable solution to produce poly-Si TFTs using a-Si TFT lines.

• Journal of the Korean Applied Science and Technology
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• v.32 no.4
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• pp.718-723
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• 2015

For the fabrication of the Si negative electrode in Li-ion batteries (LIBs) containing the cross-linking polymer binder, in this work, the urethane acrylate (UA) oligomer was synthesized via a simple synthetic process. The cross-linked poly(urethane acrylate) (CPUA)/carbone black (CB)/Si composite (CPUA/CB/Si composite) was fabricated through reactions between their reactive vinyl segments in the UA oligomer. Interestingly, the CPUA/CB/Si composite showed better cycle performance than the poly(vinylidene fluoride) (PVdF)/CB/Si composite (PVdF/CB/Si composite) and the polyurethane (PU)/CB/Si composite (PU/CB/Si composite). The CPUA/CB/Si composite had the best lithiation of about $2586mAh\;g^{-1}$. The UA oligomer showed a good compatibility with the electrode materials and current collector after and before a curing process.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.331-337
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• 2014

Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.219-219
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• 2010

Silicides have been commonly used in the Si technology due to the compatibility with Si. Recently the silicide has been applied in solar cells [1] and nanoscale interconnects [2]. The modulation of Ni silicide phase is an important issue to satisfy the needs. The excellent electric-conductive nickel monosilicide (NiSi) nanowire has proven the low resistive nanoscale interconnects. Otherwise the Ni disilicide (NiSi2) provides a template to grow a crystalline Si film above it by the little lattice mismatch of 0.4% between Si and NiSi2. We present the formation of Ni silicide phases performed by the single deposition and the co-deposition methods. The co-deposition of Ni and Si provides a stable Ni silicide phase at a reduced processing temperature comparing to the single deposition method. It also discusses the Schottky contact formation between the Ni silicide and the grown crystalline Si film for the solar cell application.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.64.2-64.2
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• 2011

Recently, Silicon Germanium (SiGe) alloys have been received considerable attention for their great potentials in advanced electronic and optoelectronic devices. Especially, microcrystalline SiGe is a good channel material for thin film transistor due to its advantages such as narrow and variable band gap and process compatibility with Si based integrated circuits. In this work, microcrystalline silicon-germanium films (${\mu}c$-SiGe) were deposited by DC/RF magnetron co-sputtering method using Si and Ge target on Corning glass substrates. The film composition was controlled by changing DC and RF powers applied to each target. The substrate temperatures were changed from $100^{\circ}C$ to $450^{\circ}C$. The microstructure of the thin films was analyzed by x-ray diffraction (XRD) and Raman spectroscopy. The analysis results showed that the crystallinity of the films enhances with increasing Ge mole fraction. Also, crystallization temperature was reduced to $300^{\circ}C$ with $H_2$ dilution. Hall measurements indicated that the electrical properties were improved by Ge alloying.

• Journal of the Korean Vacuum Society
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• v.15 no.3
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• pp.273-279
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• 2006

This study explored the possibility of porous Si (PS) formed by indirect electrode anodization used for effective isolation material for radio frequency integrated circuits (RFIC). We investigated the effect of current density and reaction time on the porosity size and depth, and X-ray diffraction of bulk Si and porous Si to evaluate the change in lattice parameter. Porosity size and depth usually increases with an increase in the current density and reaction time. PS increases the lattice parameter of Si compared to the bulk Si which causes the compressive stress of around 8 MPa. PS formed by the method is believed to be suitable for isolation material for RFIC because it is simple process as well as good compatibility to Si VLSI process.