• 한국진공학회지
• /
• 제16권5호
• /
• pp.366-370
• /
• 2007

밀도가 높고 주기적으로 배열된 나노 크기의 기공이 25nm 두께의 실리콘 산화막 기판위에 형성 되었다. 나노미터 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성하였다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 나노크기의 마스크를 만들었다. 폴리스티렌으로 이루어진 나노패턴의 지름은 $8{\sim}30nm$ 였고 높이는 40nm였으며, 패턴과 패턴사이의 간격은 60nm였다. 형성된 패턴을 실리콘 산화막 위에 전사시키기 위해 불소 기반의 화학 반응성 식각을 사용하였다. 실리콘 산화막에 형성된 기공의 지름은 $9{\sim}33nm$였다. 실리콘 산화막을 불산으로 제거하여 실리콘에 형성된 기공을 관찰하였고, 실리콘기판에 형성된 기공의 지름은 $6{\sim}22nm$였다. 형성된 기공의 크기는 폴리메틸메타아크릴레이트의 분자량과 관계가 있음을 알 수 있었다.

• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2009년도 춘계학술대회 논문집
• /
• pp.239-241
• /
• 2009

DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

• KSTLE International Journal
• /
• 제9권1_2호
• /
• pp.10-12
• /
• 2008

Silicon micro-patterns were fabricated on Si (100) wafers using photolithography and DRIE (Deep Reactive Ion Etching) fabrication techniques. The patterned shapes included micro-pillars and micro-channels. After the fabrication of the patterns, the patterned surfaces were chemically modified by coating Z-DOL (perfluoropolyether, PFPE) thin films. The surfaces were then evaluated for their micro-friction behavior in comparison with those of bare Si (100) flat, Z-DOL coated Si (100) flat and uncoated Si patterns. Experimental results showed that the chemically treated (Z-DOL coated) patterned surfaces exhibited the lowest values of coefficient of friction when compared to the rest of the test materials. The results indicate that a combination of both the topographical and chemical modification is very effective in reducing the friction property. Combined surface treatments such as these could be useful for tribological applications in miniaturized devices such as Micro/Nano-Electro-Mechanical-Systems (MEMS/NEMS).

• KSTLE International Journal
• /
• 제8권2호
• /
• pp.26-28
• /
• 2007

Si(100) surfaces were topographically modified i.e. the surfaces were patterned at micro-scale using photolithography and DRIE (Deep Reactive Ion Etching) fabrication techniques. The patterned shapes included micro-pillars and microchannels. After the fabrication of the patterns, the patterned surfaces were chemically modified by coating a thin DLC film. The surfaces were then evaluated for their friction behavior at micro-scale in comparison with those of bare Si(100) flat, DLC coated Si(100) flat and uncoated patterned surfaces. Experimental results showed that the chemically treated (DLC coated) patterned surfaces exhibited the lowest values of coefficient of friction when compared to the rest of the surfaces. This indicates that a combination of both the topographical and chemical modification is very effective in reducing the friction property. Combined surface treatments such as these could be useful for tribological applications in miniaturized devices such as Micro-Electro-Mechanical-Systems (MEMS).

• 반도체디스플레이기술학회지
• /
• 제7권1호
• /
• pp.1-5
• /
• 2008

In this paper, we fabricated pressure difference type gas flow sensor using only dry etching technology by ICP-RIE(inductive coupled plasma reactive ion etching). The sensor's structure consists of a common shear stress type piezoresistive pressure sensor with an orifice fabricated in the middle of the sensor diaphragm. Generally, structure like diaphragm is fabricated by wet etching technology using TMAH, but we fabricated diaphragm by only dry etching using ICP-RIE. To equalize the thickness of diaphragm we applied insulator($SiO_2$) layer of SOI(Si/$SiO_2$/Si-sub) wafer as delay layer of dry etching. Size of fabricated diaphragm is $1000{\times}1000{\times}7\;{\mu}m^3$ and overall chip $3000{\times}3000{\times}7\;{\mu}m^3$. We measured the variation of output voltage toward the change of gas pressure to analyze characteristics of the fabricated sensor. Sensitivity of fabricated sensor was relatively high as about 1.5mV/V kPa at 1kPa full-scale. Nonlinearity was below 0.5%F.S. Over-pressure range of the fabricated sensor is 100kPa or more.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제4C권4호
• /
• pp.149-154
• /
• 2004

This paper presents a silicon probe tip for vertical probe card application. The silicon probe tip was fabricated using MEMS technology such as porous silicon micromachining and deep- RIE (reactive ion etching). The thickness of the silicon epitaxial layers was 5 ${\mu}{\textrm}{m}$ and 7 ${\mu}{\textrm}{m}$, respectively. The width and length were 40 ${\mu}{\textrm}{m}$ and 600 ${\mu}{\textrm}{m}$, respectively. The probe structure was a multilayered structure and was composed of Au/Ni-Cr/Si$_3$N$_4$/n-epi layers. The height of the curled probe tip was measured as a function of the annealing temperature and time. Resistance characteristics of the probe tip were measured using a touchdown test.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 하계학술대회 논문집 C
• /
• pp.1890-1892
• /
• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• 마이크로전자및패키징학회지
• /
• 제18권4호
• /
• pp.49-53
• /
• 2011

TSV(through-silicon-via)를 이용한 3차원 Si 칩 패키징 공정 중 전기 도금을 이용한 비아 홀 내 Cu 고속 충전과 범핑 공정 단순화에 관하여 연구하였다. DRIE(deep reactive ion etching)법을 이용하여 TSV를 제조하였으며, 비아홀 내벽에 $SiO_2$, Ti 및 Au 기능 박막층을 형성하였다. 전도성 금속 충전에서는 비아 홀 내 Cu 충전율을 향상시키기 위하여 PPR(periodic-pulse-reverse) 전류 파형을 인가하였으며, 범프 형성 공정에서는 리소그라피(lithography) 공정을 사용하지 않는 non-PR 범핑법으로 Sn-3.5Ag 범프를 형성하였다. 전기 도금 후, 충전된 비아의 단면 및 범프의 외형을 FESEM(field emission scanning electron microscopy)으로 관찰하였다. 그 결과, Cu 충전에서는 -9.66 $mA/cm^2$의 전류밀도에서 60분간의 도금으로 비아 입구의 도금층 과성장에 의한 결함이 발생하였고, -7.71 $mA/cm^2$에서는 비아의 중간 부분에서의 도금층 과성장에 의한 결함이 발생하였다. 또한 결함이 생성된 Cu 충전물 위에 전기 도금을 이용하여 범프를 형성한 결과, 범프의 모양이 불규칙하고, 균일도가 감소함을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.418-418
• /
• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• 한국정밀공학회지
• /
• 제23권4호
• /
• pp.162-167
• /
• 2006

Hot embossing lithography(HEL) has the production advantage of comparatively few process step, simple operation, a relatively low cost for embossing tools(Si), and high replication accuracy for small features. In this paper, we considered the nano-molding characteristic according to molding parameters(temperature, pressure, times, etc) and induced a optimal molding condition using HEL. High precision nano-patter master with various shapes were designed and manufactured using the DRIE(Deep Reactive ion Etching), LPCVD(Low Pressure Chemical Vapor Deposition) and thermal oxidation process, and we investigated the molding characteristic of DVD and Blu-ray nickel stamp. We induced flow behaviors of polymer, rheology by shapes and sizes of the pattern through various molding experiments. Finally, with achieving nano-structure molding with high aspect ratio, we will secure a basic technology about the molding of large-area nano-pattern media.